Merge branch 'mesa_7_5_branch' into mesa_7_6_branch

[mesa.git] / src / gallium / drivers / nv10 / nv10_context.c

diff --git a/src/gallium/drivers/nv10/nv10_context.c b/src/gallium/drivers/nv10/nv10_context.c
index e9b61daae7f9ed0b4a8493bcb06c3cd1f2f04bcc..a127b134ecd5043369915ae96b9d90e707b70156 100644 (file)
--- a/src/gallium/drivers/nv10/nv10_context.c
+++ b/src/gallium/drivers/nv10/nv10_context.c
@@ -1,6 +1,6 @@
 #include "draw/draw_context.h"
 #include "pipe/p_defines.h"
-#include "pipe/p_winsys.h"
+#include "pipe/internal/p_winsys_screen.h"
 
 #include "nv10_context.h"
 #include "nv10_screen.h"
@@ -30,18 +30,18 @@ nv10_destroy(struct pipe_context *pipe)
 static void nv10_init_hwctx(struct nv10_context *nv10)
 {
        struct nv10_screen *screen = nv10->screen;
-       struct nouveau_winsys *nvws = screen->nvws;
+       struct nouveau_channel *chan = screen->base.channel;
        int i;
        float projectionmatrix[16];
 
        BEGIN_RING(celsius, NV10TCL_DMA_NOTIFY, 1);
        OUT_RING  (screen->sync->handle);
        BEGIN_RING(celsius, NV10TCL_DMA_IN_MEMORY0, 2);
-       OUT_RING  (nvws->channel->vram->handle);
-       OUT_RING  (nvws->channel->gart->handle);
+       OUT_RING  (chan->vram->handle);
+       OUT_RING  (chan->gart->handle);
        BEGIN_RING(celsius, NV10TCL_DMA_IN_MEMORY2, 2);
-       OUT_RING  (nvws->channel->vram->handle);
-       OUT_RING  (nvws->channel->vram->handle);
+       OUT_RING  (chan->vram->handle);
+       OUT_RING  (chan->vram->handle);
 
        BEGIN_RING(celsius, NV10TCL_NOP, 1);
        OUT_RING  (0);
@@ -177,7 +177,7 @@ static void nv10_init_hwctx(struct nv10_context *nv10)
        OUT_RING  (0);
        BEGIN_RING(celsius, NV10TCL_CULL_FACE_ENABLE, 1);
        OUT_RING  (0);
-       BEGIN_RING(celsius, NV10TCL_CLIP_PLANE_ENABLE(0), 8);
+       BEGIN_RING(celsius, NV10TCL_TX_GEN_S(0), 8);
        for (i=0;i<8;i++) {
                OUT_RING  (0);
        }
@@ -257,6 +257,29 @@ nv10_set_edgeflags(struct pipe_context *pipe, const unsigned *bitfield)
 {
 }
 
+static unsigned int
+nv10_is_texture_referenced( struct pipe_context *pipe,
+                           struct pipe_texture *texture,
+                           unsigned face, unsigned level)
+{
+   /**
+    * FIXME: Optimize.
+    */
+
+   return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
+}
+
+static unsigned int
+nv10_is_buffer_referenced( struct pipe_context *pipe,
+                          struct pipe_buffer *buf)
+{
+   /**
+    * FIXME: Optimize.
+    */
+
+   return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
+}
+
 struct pipe_context *
 nv10_create(struct pipe_screen *pscreen, unsigned pctx_id)
 {
@@ -282,6 +305,9 @@ nv10_create(struct pipe_screen *pscreen, unsigned pctx_id)
        nv10->pipe.clear = nv10_clear;
        nv10->pipe.flush = nv10_flush;
 
+       nv10->pipe.is_texture_referenced = nv10_is_texture_referenced;
+       nv10->pipe.is_buffer_referenced = nv10_is_buffer_referenced;
+
        nv10_init_surface_functions(nv10);
        nv10_init_state_functions(nv10);