{
switch (pf_type(format)) {
case PIPE_FORMAT_TYPE_FLOAT:
- return NV34TCL_VERTEX_ARRAY_FORMAT_TYPE_FLOAT;
+ return NV34TCL_VTXFMT_TYPE_FLOAT;
case PIPE_FORMAT_TYPE_UNORM:
- return NV34TCL_VERTEX_ARRAY_FORMAT_TYPE_UBYTE;
+ return NV34TCL_VTXFMT_TYPE_UBYTE;
default:
NOUVEAU_ERR("Unknown format 0x%08x\n", format);
- return NV40TCL_VTXFMT_TYPE_FLOAT;
+ return NV34TCL_VTXFMT_TYPE_FLOAT;
}
}
map += vb->buffer_offset + ve->src_offset;
switch (type) {
- case NV34TCL_VERTEX_ARRAY_FORMAT_TYPE_FLOAT:
+ case NV34TCL_VTXFMT_TYPE_FLOAT:
{
float *v = map;
- BEGIN_RING(rankine, NV34TCL_VERTEX_ATTR_4F_X(attrib), 4);
+ BEGIN_RING(rankine, NV34TCL_VTX_ATTR_4F_X(attrib), 4);
switch (ncomp) {
case 4:
OUT_RINGf(v[0]);
static void
nv30_vbo_arrays_update(struct nv30_context *nv30)
{
- struct nv30_vertex_program *vp = nv30->vertprog.active;
+ struct nv30_vertex_program *vp = nv30->vertprog;
uint32_t inputs, vtxfmt[16];
int hw, num_hw = 0;
struct pipe_vertex_buffer *vb;
if (!(inputs & (1 << hw))) {
- vtxfmt[hw] = NV34TCL_VERTEX_ARRAY_FORMAT_TYPE_FLOAT;
+ vtxfmt[hw] = NV34TCL_VTXFMT_TYPE_FLOAT;
continue;
}
vb = &nv30->vtxbuf[ve->vertex_buffer_index];
if (vb->pitch == 0) {
- vtxfmt[hw] = NV34TCL_VERTEX_ARRAY_FORMAT_TYPE_FLOAT;
+ vtxfmt[hw] = NV34TCL_VTXFMT_TYPE_FLOAT;
if (nv30_vbo_static_attrib(nv30, hw, ve, vb) == TRUE)
continue;
}
nv30->vb[hw].delta = vb->buffer_offset + ve->src_offset;
nv30->vb[hw].buffer = vb->buffer;
- vtxfmt[hw] = ((vb->pitch << NV34TCL_VERTEX_ARRAY_FORMAT_STRIDE_SHIFT) |
+ vtxfmt[hw] = ((vb->pitch << NV34TCL_VTXFMT_STRIDE_SHIFT) |
(nv30_vbo_ncomp(ve->src_format) <<
- NV34TCL_VERTEX_ARRAY_FORMAT_SIZE_SHIFT) |
+ NV34TCL_VTXFMT_SIZE_SHIFT) |
nv30_vbo_type(ve->src_format));
}
- BEGIN_RING(rankine, NV34TCL_VERTEX_ARRAY_FORMAT(0), num_hw);
+ BEGIN_RING(rankine, NV34TCL_VTXFMT(0), num_hw);
OUT_RINGp (vtxfmt, num_hw);
}
{
unsigned inputs;
- nv30_emit_hw_state(nv30);
+ nv30_state_validate(nv30);
+
+ nv30_state_emit(nv30);
if (nv30->dirty & NV30_NEW_ARRAYS) {
nv30_vbo_arrays_update(nv30);
inputs &= ~(1 << a);
- BEGIN_RING(rankine, NV34TCL_VERTEX_BUFFER_ADDRESS(a), 1);
+ BEGIN_RING(rankine, NV34TCL_VTXBUF_ADDRESS(a), 1);
OUT_RELOC (nv30->vb[a].buffer, nv30->vb[a].delta,
NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_LOW |
NOUVEAU_BO_OR | NOUVEAU_BO_RD, 0,
- NV34TCL_VERTEX_BUFFER_ADDRESS_DMA1);
+ NV34TCL_VTXBUF_ADDRESS_DMA1);
}
if (ib) {
- BEGIN_RING(rankine, NV40TCL_IDXBUF_ADDRESS, 2);
+ BEGIN_RING(rankine, NV34TCL_IDXBUF_ADDRESS, 2);
OUT_RELOCl(ib, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART |
NOUVEAU_BO_RD);
OUT_RELOCd(ib, ib_format, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART |
NOUVEAU_BO_RD | NOUVEAU_BO_OR,
- 0, NV40TCL_IDXBUF_FORMAT_DMA1);
+ 0, NV34TCL_IDXBUF_FORMAT_DMA1);
}
BEGIN_RING(rankine, 0x1710, 1);
BEGIN_RING(rankine, NV34TCL_VERTEX_BEGIN_END, 1);
OUT_RING (0);
- pipe->flush(pipe, 0);
+ pipe->flush(pipe, 0, NULL);
return TRUE;
}
switch (ib_size) {
case 2:
- type = NV40TCL_IDXBUF_FORMAT_TYPE_U16;
+ type = NV34TCL_IDXBUF_FORMAT_TYPE_U16;
break;
case 4:
- type = NV40TCL_IDXBUF_FORMAT_TYPE_U32;
+ type = NV34TCL_IDXBUF_FORMAT_TYPE_U32;
break;
default:
NOUVEAU_ERR("invalid idxbuf fmt %d\n", ib_size);
nr = (count & 0xff);
if (nr) {
- BEGIN_RING(rankine, NV40TCL_VB_INDEX_BATCH, 1);
+ BEGIN_RING(rankine, NV34TCL_VB_INDEX_BATCH, 1);
OUT_RING (((nr - 1) << 24) | start);
start += nr;
}
nr -= push;
- BEGIN_RING_NI(rankine, NV40TCL_VB_INDEX_BATCH, push);
+ BEGIN_RING_NI(rankine, NV34TCL_VB_INDEX_BATCH, push);
while (push--) {
OUT_RING(((0x100 - 1) << 24) | start);
start += 0x100;
mode, start, count);
}
- pipe->flush(pipe, 0);
+ pipe->flush(pipe, 0, NULL);
return TRUE;
}