Merge remote branch 'origin/mesa_7_6_branch'

[mesa.git] / src / gallium / drivers / nv40 / nv40_fragprog.c

diff --git a/src/gallium/drivers/nv40/nv40_fragprog.c b/src/gallium/drivers/nv40/nv40_fragprog.c
index 91dcbebda0d03723efbb6a4167b91e9a75452cf1..99277506fc207dddcfa6e89279269d35be76a6e8 100644 (file)
--- a/src/gallium/drivers/nv40/nv40_fragprog.c
+++ b/src/gallium/drivers/nv40/nv40_fragprog.c
@@ -1,6 +1,7 @@
 #include "pipe/p_context.h"
 #include "pipe/p_defines.h"
 #include "pipe/p_state.h"
+#include "pipe/p_inlines.h"
 
 #include "pipe/p_shader_tokens.h"
 #include "tgsi/tgsi_parse.h"
@@ -320,38 +321,23 @@ src_native_swz(struct nv40_fpc *fpc, const struct tgsi_full_src_register *fsrc,
 {
        const struct nv40_sreg none = nv40_sr(NV40SR_NONE, 0);
        struct nv40_sreg tgsi = tgsi_src(fpc, fsrc);
-       uint mask = 0, zero_mask = 0, one_mask = 0, neg_mask = 0;
-       uint neg[4] = { fsrc->SrcRegisterExtSwz.NegateX,
-                       fsrc->SrcRegisterExtSwz.NegateY,
-                       fsrc->SrcRegisterExtSwz.NegateZ,
-                       fsrc->SrcRegisterExtSwz.NegateW };
+       uint mask = 0;
        uint c;
 
        for (c = 0; c < 4; c++) {
-               switch (tgsi_util_get_full_src_register_extswizzle(fsrc, c)) {
-               case TGSI_EXTSWIZZLE_X:
-               case TGSI_EXTSWIZZLE_Y:
-               case TGSI_EXTSWIZZLE_Z:
-               case TGSI_EXTSWIZZLE_W:
+               switch (tgsi_util_get_full_src_register_swizzle(fsrc, c)) {
+               case TGSI_SWIZZLE_X:
+               case TGSI_SWIZZLE_Y:
+               case TGSI_SWIZZLE_Z:
+               case TGSI_SWIZZLE_W:
                        mask |= (1 << c);
                        break;
-               case TGSI_EXTSWIZZLE_ZERO:
-                       zero_mask |= (1 << c);
-                       tgsi.swz[c] = SWZ_X;
-                       break;
-               case TGSI_EXTSWIZZLE_ONE:
-                       one_mask |= (1 << c);
-                       tgsi.swz[c] = SWZ_X;
-                       break;
                default:
                        assert(0);
                }
-
-               if (!tgsi.negate && neg[c])
-                       neg_mask |= (1 << c);
        }
 
-       if (mask == MASK_ALL && !neg_mask)
+       if (mask == MASK_ALL)
                return TRUE;
 
        *src = temp(fpc);
@@ -359,18 +345,6 @@ src_native_swz(struct nv40_fpc *fpc, const struct tgsi_full_src_register *fsrc,
        if (mask)
                arith(fpc, 0, MOV, *src, mask, tgsi, none, none);
 
-       if (zero_mask)
-               arith(fpc, 0, SFL, *src, zero_mask, *src, none, none);
-
-       if (one_mask)
-               arith(fpc, 0, STR, *src, one_mask, *src, none, none);
-
-       if (neg_mask) {
-               struct nv40_sreg one = temp(fpc);
-               arith(fpc, 0, STR, one, neg_mask, one, none, none);
-               arith(fpc, 0, MUL, *src, neg_mask, *src, neg(one), none);
-       }
-
        return FALSE;
 }
 
@@ -567,12 +541,6 @@ nv40_fragprog_parse_instruction(struct nv40_fpc *fpc,
        case TGSI_OPCODE_MUL:
                arith(fpc, sat, MUL, dst, mask, src[0], src[1], none);
                break;
-       case TGSI_OPCODE_NOISE1:
-       case TGSI_OPCODE_NOISE2:
-       case TGSI_OPCODE_NOISE3:
-       case TGSI_OPCODE_NOISE4:
-               arith(fpc, sat, SFL, dst, mask, none, none, none);
-               break;
        case TGSI_OPCODE_POW:
                tmp = temp(fpc);
                arith(fpc, 0, LG2, tmp, MASK_X,
@@ -789,10 +757,10 @@ nv40_fragprog_prepare(struct nv40_fpc *fpc)
                        assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
                        assert(fpc->nr_imm < MAX_IMM);
 
-                       vals[0] = imm->u.ImmediateFloat32[0].Float;
-                       vals[1] = imm->u.ImmediateFloat32[1].Float;
-                       vals[2] = imm->u.ImmediateFloat32[2].Float;
-                       vals[3] = imm->u.ImmediateFloat32[3].Float;
+                       vals[0] = imm->u[0].Float;
+                       vals[1] = imm->u[1].Float;
+                       vals[2] = imm->u[2].Float;
+                       vals[3] = imm->u[3].Float;
                        fpc->imm[fpc->nr_imm++] = constant(fpc, -1, vals);
                }
                        break;
@@ -881,12 +849,12 @@ static void
 nv40_fragprog_upload(struct nv40_context *nv40,
                     struct nv40_fragment_program *fp)
 {
-       struct pipe_winsys *ws = nv40->pipe.winsys;
+       struct pipe_screen *pscreen = nv40->pipe.screen;
        const uint32_t le = 1;
        uint32_t *map;
        int i;
 
-       map = ws->buffer_map(ws, fp->buffer, PIPE_BUFFER_USAGE_CPU_WRITE);
+       map = pipe_buffer_map(pscreen, fp->buffer, PIPE_BUFFER_USAGE_CPU_WRITE);
 
 #if 0
        for (i = 0; i < fp->insn_len; i++) {
@@ -908,7 +876,7 @@ nv40_fragprog_upload(struct nv40_context *nv40,
                }
        }
 
-       ws->buffer_unmap(ws, fp->buffer);
+       pipe_buffer_unmap(pscreen, fp->buffer);
 }
 
 static boolean
@@ -917,7 +885,7 @@ nv40_fragprog_validate(struct nv40_context *nv40)
        struct nv40_fragment_program *fp = nv40->fragprog;
        struct pipe_buffer *constbuf =
                nv40->constbuf[PIPE_SHADER_FRAGMENT];
-       struct pipe_winsys *ws = nv40->pipe.winsys;
+       struct pipe_screen *pscreen = nv40->pipe.screen;
        struct nouveau_stateobj *so;
        boolean new_consts = FALSE;
        int i;
@@ -932,23 +900,26 @@ nv40_fragprog_validate(struct nv40_context *nv40)
                return FALSE;
        }
 
-       fp->buffer = ws->buffer_create(ws, 0x100, 0, fp->insn_len * 4);
+       fp->buffer = pscreen->buffer_create(pscreen, 0x100, 0, fp->insn_len * 4);
        nv40_fragprog_upload(nv40, fp);
 
        so = so_new(4, 1);
        so_method(so, nv40->screen->curie, NV40TCL_FP_ADDRESS, 1);
-       so_reloc (so, fp->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART |
-                 NOUVEAU_BO_RD | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
-                 NV40TCL_FP_ADDRESS_DMA0, NV40TCL_FP_ADDRESS_DMA1);
+       so_reloc (so, nouveau_bo(fp->buffer), 0, NOUVEAU_BO_VRAM |
+                     NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
+                     NOUVEAU_BO_OR, NV40TCL_FP_ADDRESS_DMA0,
+                     NV40TCL_FP_ADDRESS_DMA1);
        so_method(so, nv40->screen->curie, NV40TCL_FP_CONTROL, 1);
        so_data  (so, fp->fp_control);
        so_ref(so, &fp->so);
+       so_ref(NULL, &so);
 
 update_constants:
        if (fp->nr_consts) {
                float *map;
                
-               map = ws->buffer_map(ws, constbuf, PIPE_BUFFER_USAGE_CPU_READ);
+               map = pipe_buffer_map(pscreen, constbuf,
+                                     PIPE_BUFFER_USAGE_CPU_READ);
                for (i = 0; i < fp->nr_consts; i++) {
                        struct nv40_fragment_program_data *fpd = &fp->consts[i];
                        uint32_t *p = &fp->insn[fpd->offset];
@@ -959,7 +930,7 @@ update_constants:
                        memcpy(p, cb, 4 * sizeof(float));
                        new_consts = TRUE;
                }
-               ws->buffer_unmap(ws, constbuf);
+               pipe_buffer_unmap(pscreen, constbuf);
 
                if (new_consts)
                        nv40_fragprog_upload(nv40, fp);