r300: respect radeon common code fallbacks

[mesa.git] / src / gallium / drivers / nv40 / nv40_vertprog.c

diff --git a/src/gallium/drivers/nv40/nv40_vertprog.c b/src/gallium/drivers/nv40/nv40_vertprog.c
index d9fc31006f5aff7562c4204a828a3efa4e2cb07f..c93c5d127c44d634f97e8e0193dddb547d85a85d 100644 (file)
--- a/src/gallium/drivers/nv40/nv40_vertprog.c
+++ b/src/gallium/drivers/nv40/nv40_vertprog.c
@@ -1,7 +1,7 @@
 #include "pipe/p_context.h"
 #include "pipe/p_defines.h"
 #include "pipe/p_state.h"
-#include "pipe/p_inlines.h"
+#include "util/u_inlines.h"
 
 #include "pipe/p_shader_tokens.h"
 #include "tgsi/tgsi_parse.h"
@@ -742,7 +742,7 @@ nv40_vertprog_translate(struct nv40_context *nv40,
        }
 
        /* Redirect post-transform vertex position to a temp if user clip
-        * planes are enabled.  We need to append code the the vtxprog
+        * planes are enabled.  We need to append code to the vtxprog
         * to handle clip planes later.
         */
        if (vp->ucp.nr)  {
@@ -834,7 +834,9 @@ static boolean
 nv40_vertprog_validate(struct nv40_context *nv40)
 { 
        struct pipe_screen *pscreen = nv40->pipe.screen;
-       struct nouveau_grobj *curie = nv40->screen->curie;
+       struct nv40_screen *screen = nv40->screen;
+       struct nouveau_channel *chan = screen->base.channel;
+       struct nouveau_grobj *curie = screen->curie;
        struct nv40_vertex_program *vp;
        struct pipe_buffer *constbuf;
        boolean upload_code = FALSE, upload_data = FALSE;
@@ -884,7 +886,7 @@ check_gpu_resources:
                                assert(0);
                }
 
-               so = so_new(7, 0);
+               so = so_new(3, 4, 0);
                so_method(so, curie, NV40TCL_VP_START_FROM_ID, 1);
                so_data  (so, vp->exec->start);
                so_method(so, curie, NV40TCL_VP_ATTRIB_EN, 2);
@@ -974,9 +976,9 @@ check_gpu_resources:
                                       4 * sizeof(float));
                        }
 
-                       BEGIN_RING(curie, NV40TCL_VP_UPLOAD_CONST_ID, 5);
-                       OUT_RING  (i + vp->data->start);
-                       OUT_RINGp ((uint32_t *)vpd->value, 4);
+                       BEGIN_RING(chan, curie, NV40TCL_VP_UPLOAD_CONST_ID, 5);
+                       OUT_RING  (chan, i + vp->data->start);
+                       OUT_RINGp (chan, (uint32_t *)vpd->value, 4);
                }
 
                if (constbuf)
@@ -993,11 +995,11 @@ check_gpu_resources:
                        NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[3]);
                }
 #endif
-               BEGIN_RING(curie, NV40TCL_VP_UPLOAD_FROM_ID, 1);
-               OUT_RING  (vp->exec->start);
+               BEGIN_RING(chan, curie, NV40TCL_VP_UPLOAD_FROM_ID, 1);
+               OUT_RING  (chan, vp->exec->start);
                for (i = 0; i < vp->nr_insns; i++) {
-                       BEGIN_RING(curie, NV40TCL_VP_UPLOAD_INST(0), 4);
-                       OUT_RINGp (vp->insns[i].data, 4);
+                       BEGIN_RING(chan, curie, NV40TCL_VP_UPLOAD_INST(0), 4);
+                       OUT_RINGp (chan, vp->insns[i].data, 4);
                }
        }