nv50/ir: Rename "mkLoad" to "mkLoadv" for consistency.

[mesa.git] / src / gallium / drivers / nv50 / codegen / nv50_ir_ra.cpp

diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
index 7e3291db41734c81a5ebaaa912b6b406382228e9..e0fea4b933754e6f5e8d3be5b3d47f20c35c1528 100644 (file)
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
@@ -1586,6 +1586,13 @@ RegAlloc::execFunc()
    unsigned int i, retries;
    bool ret;
 
+   if (!func->ins.empty()) {
+      // Insert a nop at the entry so inputs only used by the first instruction
+      // don't count as having an empty live range.
+      Instruction *nop = new_Instruction(func, OP_NOP, TYPE_NONE);
+      BasicBlock::get(func->cfg.getRoot())->insertHead(nop);
+   }
+
    ret = insertConstr.exec(func);
    if (!ret)
       goto out;
@@ -1955,7 +1962,9 @@ RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb)
          if (i->src(0).isIndirect(0) && typeSizeof(i->dType) >= 8)
             addHazard(i, i->src(0).getIndirect(0));
       } else
-      if (i->op == OP_UNION) {
+      if (i->op == OP_UNION ||
+          i->op == OP_MERGE ||
+          i->op == OP_SPLIT) {
          constrList.push_back(i);
       }
    }