#include "util/u_transfer.h"
#include "util/u_double_list.h"
-#define NOUVEAU_NVC0
-#include "nouveau/nouveau_winsys.h"
-#undef NOUVEAU_NVC0
-
-struct pipe_resource;
-struct nouveau_bo;
-struct nv50_context;
-
-#define NV50_BUFFER_SCORE_MIN -25000
-#define NV50_BUFFER_SCORE_MAX 25000
-#define NV50_BUFFER_SCORE_VRAM_THRESHOLD 20000
-
-/* DIRTY: buffer was (or will be after the next flush) written to by GPU and
- * resource->data has not been updated to reflect modified VRAM contents
- *
- * USER_MEMORY: resource->data is a pointer to client memory and may change
- * between GL calls
- */
-#define NV50_BUFFER_STATUS_DIRTY (1 << 0)
-#define NV50_BUFFER_STATUS_USER_MEMORY (1 << 7)
-
-/* Resources, if mapped into the GPU's address space, are guaranteed to
- * have constant virtual addresses.
- * The address of a resource will lie within the nouveau_bo referenced,
- * and this bo should be added to the memory manager's validation list.
- */
-struct nv50_resource {
- struct pipe_resource base;
- const struct u_resource_vtbl *vtbl;
-
- uint8_t *data;
- struct nouveau_bo *bo;
- uint32_t offset;
- uint8_t status;
- uint8_t domain;
-
- int16_t score; /* low if mapped very often, if high can move to VRAM */
-
- struct nouveau_fence *fence;
- struct nouveau_fence *fence_wr;
+#include "nouveau/nouveau_winsys.h"
+#include "nouveau/nouveau_buffer.h"
- struct nouveau_mm_allocation *mm;
-};
+#ifndef __NVC0_RESOURCE_H__ /* make sure we don't use these in nvc0: */
void
-nv50_buffer_release_gpu_storage(struct nv50_resource *);
-
-boolean
-nv50_buffer_download(struct nv50_context *, struct nv50_resource *,
- unsigned start, unsigned size);
-
-boolean
-nv50_buffer_migrate(struct nv50_context *,
- struct nv50_resource *, unsigned domain);
-
-static INLINE void
-nv50_buffer_adjust_score(struct nv50_context *nv50, struct nv50_resource *res,
- int16_t score)
-{
- if (score < 0) {
- if (res->score > NV50_BUFFER_SCORE_MIN)
- res->score += score;
- } else
- if (score > 0){
- if (res->score < NV50_BUFFER_SCORE_MAX)
- res->score += score;
- if (res->domain == NOUVEAU_BO_GART &&
- res->score > NV50_BUFFER_SCORE_VRAM_THRESHOLD)
- nv50_buffer_migrate(nv50, res, NOUVEAU_BO_VRAM);
- }
-}
-
-/* XXX: wait for fence (atm only using this for vertex push) */
-static INLINE void *
-nv50_resource_map_offset(struct nv50_context *nv50,
- struct nv50_resource *res, uint32_t offset,
- uint32_t flags)
-{
- void *map;
-
- nv50_buffer_adjust_score(nv50, res, -250);
-
- if ((res->domain == NOUVEAU_BO_VRAM) &&
- (res->status & NV50_BUFFER_STATUS_DIRTY))
- nv50_buffer_download(nv50, res, 0, res->base.width0);
-
- if ((res->domain != NOUVEAU_BO_GART) ||
- (res->status & NV50_BUFFER_STATUS_USER_MEMORY))
- return res->data + offset;
+nv50_init_resource_functions(struct pipe_context *pcontext);
- if (res->mm)
- flags |= NOUVEAU_BO_NOSYNC;
+void
+nv50_screen_init_resource_functions(struct pipe_screen *pscreen);
- if (nouveau_bo_map_range(res->bo, res->offset + offset,
- res->base.width0, flags))
- return NULL;
+#define NV50_RESOURCE_FLAG_VIDEO (NOUVEAU_RESOURCE_FLAG_DRV_PRIV << 0)
- map = res->bo->map;
- nouveau_bo_unmap(res->bo);
- return map;
-}
+#define NV50_TILE_SHIFT_X(m) 6
+#define NV50_TILE_SHIFT_Y(m) ((((m) >> 4) & 0xf) + 2)
+#define NV50_TILE_SHIFT_Z(m) ((((m) >> 8) & 0xf) + 0)
-static INLINE void
-nv50_resource_unmap(struct nv50_resource *res)
-{
- /* no-op */
-}
+#define NV50_TILE_SIZE_X(m) 64
+#define NV50_TILE_SIZE_Y(m) ( 4 << (((m) >> 4) & 0xf))
+#define NV50_TILE_SIZE_Z(m) ( 1 << (((m) >> 8) & 0xf))
-#define NV50_TILE_DIM_SHIFT(m, d) (((m) >> (d * 4)) & 0xf)
+#define NV50_TILE_SIZE_2D(m) (NV50_TILE_SIZE_X(m) << NV50_TILE_SHIFT_Y(m))
-#define NV50_TILE_PITCH(m) (64 << 0)
-#define NV50_TILE_HEIGHT(m) ( 4 << NV50_TILE_DIM_SHIFT(m, 0))
-#define NV50_TILE_DEPTH(m) ( 1 << NV50_TILE_DIM_SHIFT(m, 1))
+#define NV50_TILE_SIZE(m) (NV50_TILE_SIZE_2D(m) << NV50_TILE_SHIFT_Z(m))
-#define NV50_TILE_SIZE_2D(m) ((64 * 8) << \
- NV50_TILE_DIM_SHIFT(m, 0))
+#endif /* __NVC0_RESOURCE_H__ */
-#define NV50_TILE_SIZE(m) (NV50_TILE_SIZE_2D(m) << NV50_TILE_DIM_SHIFT(m, 1))
+uint32_t
+nv50_tex_choose_tile_dims_helper(unsigned nx, unsigned ny, unsigned nz);
struct nv50_miptree_level {
uint32_t offset;
#define NV50_MAX_TEXTURE_LEVELS 16
struct nv50_miptree {
- struct nv50_resource base;
+ struct nv04_resource base;
struct nv50_miptree_level level[NV50_MAX_TEXTURE_LEVELS];
uint32_t total_size;
uint32_t layer_stride;
boolean layout_3d; /* TRUE if layer count varies with mip level */
+ uint8_t ms_x; /* log2 of number of samples in x/y dimension */
+ uint8_t ms_y;
+ uint8_t ms_mode;
};
static INLINE struct nv50_miptree *
return (struct nv50_miptree *)pt;
}
-static INLINE struct nv50_resource *
-nv50_resource(struct pipe_resource *resource)
-{
- return (struct nv50_resource *)resource;
-}
-
-/* is resource mapped into the GPU's address space (i.e. VRAM or GART) ? */
-static INLINE boolean
-nv50_resource_mapped_by_gpu(struct pipe_resource *resource)
-{
- return nv50_resource(resource)->domain != 0;
-}
-void
-nv50_init_resource_functions(struct pipe_context *pcontext);
+#define NV50_TEXVIEW_SCALED_COORDS (1 << 0)
+#define NV50_TEXVIEW_FILTER_MSAA8 (1 << 1)
+#define NV50_TEXVIEW_ACCESS_RESOLVE (1 << 2)
-void
-nv50_screen_init_resource_functions(struct pipe_screen *pscreen);
/* Internal functions:
*/
+boolean
+nv50_miptree_init_layout_linear(struct nv50_miptree *mt, unsigned pitch_align);
+
struct pipe_resource *
nv50_miptree_create(struct pipe_screen *pscreen,
const struct pipe_resource *tmp);
+void
+nv50_miptree_destroy(struct pipe_screen *pscreen, struct pipe_resource *pt);
+
struct pipe_resource *
nv50_miptree_from_handle(struct pipe_screen *pscreen,
const struct pipe_resource *template,
struct winsys_handle *whandle);
-struct pipe_resource *
-nv50_buffer_create(struct pipe_screen *pscreen,
- const struct pipe_resource *templ);
+boolean
+nv50_miptree_get_handle(struct pipe_screen *pscreen,
+ struct pipe_resource *pt,
+ struct winsys_handle *whandle);
-struct pipe_resource *
-nv50_user_buffer_create(struct pipe_screen *screen,
- void *ptr,
- unsigned bytes,
- unsigned usage);
+struct nv50_surface {
+ struct pipe_surface base;
+ uint32_t offset;
+ uint32_t width;
+ uint16_t height;
+ uint16_t depth;
+};
+
+static INLINE struct nv50_surface *
+nv50_surface(struct pipe_surface *ps)
+{
+ return (struct nv50_surface *)ps;
+}
+
+static INLINE enum pipe_format
+nv50_zs_to_s_format(enum pipe_format format)
+{
+ switch (format) {
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT: return PIPE_FORMAT_X24S8_UINT;
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM: return PIPE_FORMAT_S8X24_UINT;
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: return PIPE_FORMAT_X32_S8X24_UINT;
+ default:
+ return format;
+ }
+}
+#ifndef __NVC0_RESOURCE_H__
+
+unsigned
+nv50_mt_zslice_offset(const struct nv50_miptree *mt, unsigned l, unsigned z);
struct pipe_surface *
nv50_miptree_surface_new(struct pipe_context *,
struct pipe_resource *,
const struct pipe_surface *templ);
+void *
+nv50_miptree_transfer_map(struct pipe_context *pctx,
+ struct pipe_resource *res,
+ unsigned level,
+ unsigned usage,
+ const struct pipe_box *box,
+ struct pipe_transfer **ptransfer);
void
-nv50_miptree_surface_del(struct pipe_context *, struct pipe_surface *);
+nv50_miptree_transfer_unmap(struct pipe_context *pcontext,
+ struct pipe_transfer *ptx);
-boolean
-nv50_user_buffer_upload(struct nv50_resource *, unsigned base, unsigned size);
+#endif /* __NVC0_RESOURCE_H__ */
+
+struct nv50_surface *
+nv50_surface_from_miptree(struct nv50_miptree *mt,
+ const struct pipe_surface *templ);
+
+struct pipe_surface *
+nv50_surface_from_buffer(struct pipe_context *pipe,
+ struct pipe_resource *pt,
+ const struct pipe_surface *templ);
+
+void
+nv50_surface_destroy(struct pipe_context *, struct pipe_surface *);
-#endif
+#endif /* __NV50_RESOURCE_H__ */
projects / mesa.git / blobdiff