Merge branch 'gallium-0.2' into gallium-winsys-private
[mesa.git] / src / gallium / drivers / nv50 / nv50_screen.c
index 29c057a14535be64bcf13a44dc755844487109c2..3abacfc8d544b4de6fc01c106ef84e2a7aeed5b5 100644 (file)
@@ -1,5 +1,26 @@
+/*
+ * Copyright 2008 Ben Skeggs
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
 #include "pipe/p_screen.h"
-#include "pipe/p_util.h"
 
 #include "nv50_context.h"
 #include "nv50_screen.h"
 #include "nouveau/nouveau_stateobj.h"
 
 #define NV5X_GRCLASS5097_CHIPSETS 0x00000001
-#define NV8X_GRCLASS8297_CHIPSETS 0x00000010
-#define NV9X_GRCLASS8297_CHIPSETS 0x00000004
+#define NV8X_GRCLASS8297_CHIPSETS 0x00000050
+#define NV9X_GRCLASS8297_CHIPSETS 0x00000014
 
 static boolean
 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
-                               enum pipe_format format, uint type)
+                               enum pipe_format format,
+                               enum pipe_texture_target target,
+                               unsigned tex_usage, unsigned geom_flags)
 {
-       switch (type) {
-       case PIPE_SURFACE:
+       if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
                switch (format) {
                case PIPE_FORMAT_A8R8G8B8_UNORM:
                case PIPE_FORMAT_R5G6B5_UNORM:
@@ -25,17 +47,24 @@ nv50_screen_is_format_supported(struct pipe_screen *pscreen,
                default:
                        break;
                }
-               break;
-       case PIPE_TEXTURE:
+       } else {
                switch (format) {
+               case PIPE_FORMAT_A8R8G8B8_UNORM:
+               case PIPE_FORMAT_A1R5G5B5_UNORM:
+               case PIPE_FORMAT_A4R4G4B4_UNORM:
+               case PIPE_FORMAT_R5G6B5_UNORM:
+               case PIPE_FORMAT_L8_UNORM:
+               case PIPE_FORMAT_A8_UNORM:
                case PIPE_FORMAT_I8_UNORM:
+               case PIPE_FORMAT_A8L8_UNORM:
+               case PIPE_FORMAT_DXT1_RGB:
+               case PIPE_FORMAT_DXT1_RGBA:
+               case PIPE_FORMAT_DXT3_RGBA:
+               case PIPE_FORMAT_DXT5_RGBA:
                        return TRUE;
                default:
                        break;
                }
-               break;
-       default:
-               assert(0);
        }
 
        return FALSE;
@@ -65,30 +94,36 @@ nv50_screen_get_param(struct pipe_screen *pscreen, int param)
        case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
                return 32;
        case PIPE_CAP_NPOT_TEXTURES:
-               return 0;
+               return 1;
        case PIPE_CAP_TWO_SIDED_STENCIL:
                return 1;
        case PIPE_CAP_GLSL:
                return 0;
        case PIPE_CAP_S3TC:
-               return 0;
+               return 1;
        case PIPE_CAP_ANISOTROPIC_FILTER:
-               return 0;
+               return 1;
        case PIPE_CAP_POINT_SPRITE:
                return 0;
        case PIPE_CAP_MAX_RENDER_TARGETS:
                return 8;
        case PIPE_CAP_OCCLUSION_QUERY:
-               return 0;
+               return 1;
        case PIPE_CAP_TEXTURE_SHADOW_MAP:
-               return 0;
+               return 1;
        case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
                return 13;
        case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
                return 10;
        case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
                return 13;
+       case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
+       case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
+               return 1;
+       case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
+               return 0;
        case NOUVEAU_CAP_HW_VTXBUF:     
+               return 1;
        case NOUVEAU_CAP_HW_IDXBUF:     
                return 0;
        default:
@@ -117,28 +152,6 @@ nv50_screen_get_paramf(struct pipe_screen *pscreen, int param)
        }
 }
 
-static void *
-nv50_surface_map(struct pipe_screen *screen, struct pipe_surface *surface,
-                unsigned flags )
-{
-       struct pipe_winsys *ws = screen->winsys;
-       void *map;
-
-       map = ws->buffer_map(ws, surface->buffer, flags);
-       if (!map)
-               return NULL;
-
-       return map + surface->offset;
-}
-
-static void
-nv50_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface)
-{
-       struct pipe_winsys *ws = screen->winsys;
-
-       ws->buffer_unmap(ws, surface->buffer);
-}
-
 static void
 nv50_screen_destroy(struct pipe_screen *pscreen)
 {
@@ -204,20 +217,97 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
        }
 
        /* Static tesla init */
-       so = so_new(128, 0);
+       so = so_new(256, 20);
+
+       so_method(so, screen->tesla, 0x1558, 1);
+       so_data  (so, 1);
        so_method(so, screen->tesla, NV50TCL_DMA_NOTIFY, 1);
        so_data  (so, screen->sync->handle);
-       so_method(so, screen->tesla, NV50TCL_DMA_IN_MEMORY0(0),
-                 NV50TCL_DMA_IN_MEMORY0__SIZE);
-       for (i = 0; i < NV50TCL_DMA_IN_MEMORY0__SIZE; i++)
+       so_method(so, screen->tesla, NV50TCL_DMA_UNK0(0),
+                                    NV50TCL_DMA_UNK0__SIZE);
+       for (i = 0; i < NV50TCL_DMA_UNK0__SIZE; i++)
                so_data(so, nvws->channel->vram->handle);
-       so_method(so, screen->tesla, NV50TCL_DMA_IN_MEMORY1(0),
-                 NV50TCL_DMA_IN_MEMORY1__SIZE);
-       for (i = 0; i < NV50TCL_DMA_IN_MEMORY1__SIZE; i++)
+       so_method(so, screen->tesla, NV50TCL_DMA_UNK1(0),
+                                    NV50TCL_DMA_UNK1__SIZE);
+       for (i = 0; i < NV50TCL_DMA_UNK1__SIZE; i++)
                so_data(so, nvws->channel->vram->handle);
+       so_method(so, screen->tesla, 0x121c, 1);
+       so_data  (so, 1);
+
+       so_method(so, screen->tesla, 0x13bc, 1);
+       so_data  (so, 0x54);
+       so_method(so, screen->tesla, 0x13ac, 1);
+       so_data  (so, 1);
+       so_method(so, screen->tesla, 0x16b8, 1);
+       so_data  (so, 8);
+
+       /* Shared constant buffer */
+       screen->constbuf = ws->_buffer_create(ws, 0, 0, 128 * 4 * 4);
+       if (nvws->res_init(&screen->vp_data_heap, 0, 128)) {
+               NOUVEAU_ERR("Error initialising constant buffer\n");
+               nv50_screen_destroy(&screen->pipe);
+               return NULL;
+       }
+
+       so_method(so, screen->tesla, 0x1280, 3);
+       so_reloc (so, screen->constbuf, 0, NOUVEAU_BO_VRAM |
+                 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
+       so_reloc (so, screen->constbuf, 0, NOUVEAU_BO_VRAM |
+                 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
+       so_data  (so, (NV50_CB_PMISC << 16) | 0x00001000);
+
+       /* Texture sampler/image unit setup - we abuse the constant buffer
+        * upload mechanism for the moment to upload data to the tex config
+        * blocks.  At some point we *may* want to go the NVIDIA way of doing
+        * things?
+        */
+       screen->tic = ws->_buffer_create(ws, 0, 0, 32 * 8 * 4);
+       so_method(so, screen->tesla, 0x1280, 3);
+       so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
+                 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
+       so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
+                 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
+       so_data  (so, (NV50_CB_TIC << 16) | 0x0800);
+       so_method(so, screen->tesla, 0x1574, 3);
+       so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
+                 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
+       so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
+                 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
+       so_data  (so, 0x00000800);
+
+       screen->tsc = ws->_buffer_create(ws, 0, 0, 32 * 8 * 4);
+       so_method(so, screen->tesla, 0x1280, 3);
+       so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM |
+                 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
+       so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM |
+                 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
+       so_data  (so, (NV50_CB_TSC << 16) | 0x0800);
+       so_method(so, screen->tesla, 0x155c, 3);
+       so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM |
+                 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
+       so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM |
+                 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
+       so_data  (so, 0x00000800);
+
+
+       /* Vertex array limits - max them out */
+       for (i = 0; i < 16; i++) {
+               so_method(so, screen->tesla, 0x1080 + (i * 8), 2);
+               so_data  (so, 0x000000ff);
+               so_data  (so, 0xffffffff);
+       }
+
+       so_method(so, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR, 2);
+       so_data  (so, fui(0.0));
+       so_data  (so, fui(1.0));
+
+       so_method(so, screen->tesla, 0x1234, 1);
+       so_data  (so, 1);
+       so_method(so, screen->tesla, 0x1458, 1);
+       so_data  (so, 1);
 
        so_emit(nvws, so);
-       so_ref(NULL, &so);
+       so_ref(so, &screen->static_init);
        nvws->push_flush(nvws, 0, NULL);
 
        screen->pipe.winsys = ws;
@@ -231,10 +321,8 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
 
        screen->pipe.is_format_supported = nv50_screen_is_format_supported;
 
-       screen->pipe.surface_map = nv50_surface_map;
-       screen->pipe.surface_unmap = nv50_surface_unmap;
-
        nv50_screen_init_miptree_functions(&screen->pipe);
+       nv50_surface_init_screen_functions(&screen->pipe);
 
        return &screen->pipe;
 }