nv50,nvc0: activate seamless cube map filtering

[mesa.git] / src / gallium / drivers / nv50 / nv50_tex.c

diff --git a/src/gallium/drivers/nv50/nv50_tex.c b/src/gallium/drivers/nv50/nv50_tex.c
index eaee0a1107f9997fc435260efa011ccf41ef36eb..9192d2e25901a50fb4b9d920a5afbd97a445956b 100644 (file)
--- a/src/gallium/drivers/nv50/nv50_tex.c
+++ b/src/gallium/drivers/nv50/nv50_tex.c
@@ -27,8 +27,12 @@
 
 #include "util/u_format.h"
 
+#define NV50_TIC_0_SWIZZLE__MASK                      \
+   (NV50_TIC_0_MAPA__MASK | NV50_TIC_0_MAPB__MASK |   \
+    NV50_TIC_0_MAPG__MASK | NV50_TIC_0_MAPR__MASK)
+
 static INLINE uint32_t
-nv50_tic_swizzle(uint32_t tc, unsigned swz)
+nv50_tic_swizzle(uint32_t tc, unsigned swz, boolean tex_int)
 {
    switch (swz) {
    case PIPE_SWIZZLE_RED:
@@ -40,7 +44,7 @@ nv50_tic_swizzle(uint32_t tc, unsigned swz)
    case PIPE_SWIZZLE_ALPHA:
       return (tc & NV50_TIC_0_MAPA__MASK) >> NV50_TIC_0_MAPA__SHIFT;
    case PIPE_SWIZZLE_ONE:
-      return NV50_TIC_MAP_ONE;
+      return tex_int ? NV50_TIC_MAP_ONE_INT : NV50_TIC_MAP_ONE_FLOAT;
    case PIPE_SWIZZLE_ZERO:
    default:
       return NV50_TIC_MAP_ZERO;
@@ -58,6 +62,7 @@ nv50_create_sampler_view(struct pipe_context *pipe,
    uint32_t depth;
    struct nv50_tic_entry *view;
    struct nv50_miptree *mt = nv50_miptree(texture);
+   boolean tex_int;
 
    view = MALLOC_STRUCT(nv50_tic_entry);
    if (!view)
@@ -74,26 +79,28 @@ nv50_create_sampler_view(struct pipe_context *pipe,
 
    tic = &view->tic[0];
 
-   desc = util_format_description(mt->base.base.format);
+   desc = util_format_description(view->pipe.format);
 
    /* TIC[0] */
 
    tic[0] = nv50_format_table[view->pipe.format].tic;
 
-   swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r);
-   swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g);
-   swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b);
-   swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a);
+   tex_int = FALSE; /* XXX: integer textures */
+
+   swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r, tex_int);
+   swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g, tex_int);
+   swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b, tex_int);
+   swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a, tex_int);
    tic[0] = (tic[0] & ~NV50_TIC_0_SWIZZLE__MASK) |
       (swz[0] << NV50_TIC_0_MAPR__SHIFT) |
       (swz[1] << NV50_TIC_0_MAPG__SHIFT) |
       (swz[2] << NV50_TIC_0_MAPB__SHIFT) |
       (swz[3] << NV50_TIC_0_MAPA__SHIFT);
 
-   /* tic[1] = mt->base.bo->offset; */
+   tic[1] = /* mt->base.bo->offset; */ 0;
    tic[2] = /* mt->base.bo->offset >> 32 */ 0;
 
-   tic[2] |= 0x10001000 | /* NV50_TIC_2_NO_BORDER */ 0x40000000;
+   tic[2] |= 0x10001000 | NV50_TIC_2_NO_BORDER;
 
    if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
       tic[2] |= NV50_TIC_2_COLORSPACE_SRGB;
@@ -107,6 +114,12 @@ nv50_create_sampler_view(struct pipe_context *pipe,
 
    depth = MAX2(mt->base.base.array_size, mt->base.base.depth0);
 
+   if (mt->base.base.target == PIPE_TEXTURE_1D_ARRAY ||
+       mt->base.base.target == PIPE_TEXTURE_2D_ARRAY) {
+      tic[1] = view->pipe.u.tex.first_layer * mt->layer_stride;
+      depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
+   }
+
    switch (mt->base.base.target) {
    case PIPE_TEXTURE_1D:
       tic[2] |= NV50_TIC_2_TARGET_1D;
@@ -134,7 +147,8 @@ nv50_create_sampler_view(struct pipe_context *pipe,
       tic[2] |= NV50_TIC_2_TARGET_2D_ARRAY;
       break;
    case PIPE_BUFFER:
-      tic[2] |= NV50_TIC_2_TARGET_BUFFER | /* NV50_TIC_2_LINEAR */ (1 << 18);
+      tic[2] |= NV50_TIC_2_TARGET_BUFFER | NV50_TIC_2_LINEAR;
+      break;
    default:
       NOUVEAU_ERR("invalid texture target: %d\n", mt->base.base.target);
       return FALSE;
@@ -178,6 +192,8 @@ nv50_validate_tic(struct nv50_context *nv50, int s)
       res = &nv50_miptree(tic->pipe.texture)->base;
 
       if (tic->id < 0) {
+         uint32_t offset = tic->tic[1];
+
          tic->id = nv50_screen_tic_alloc(nv50->screen, tic);
 
          MARK_RING (chan, 24 + 8, 4);
@@ -206,15 +222,23 @@ nv50_validate_tic(struct nv50_context *nv50, int s)
          OUT_RING  (chan, 0);
          BEGIN_RING_NI(chan, RING_2D(SIFC_DATA), 8);
          OUT_RING  (chan, tic->tic[0]);
-         OUT_RELOCl(chan, res->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
-         OUT_RELOC (chan, res->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
+         OUT_RELOCl(chan, res->bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+         OUT_RELOC (chan, res->bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
                     NOUVEAU_BO_HIGH | NOUVEAU_BO_OR, tic->tic[2], tic->tic[2]);
          OUT_RINGp (chan, &tic->tic[3], 5);
 
          need_flush = TRUE;
+      } else
+      if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
+         BEGIN_RING(chan, RING_3D(TEX_CACHE_CTL), 1);
+         OUT_RING  (chan, 0x20); //(tic->id << 4) | 1);
       }
+
       nv50->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
 
+      res->status &= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
+      res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
+
       nv50_bufctx_add_resident(nv50, NV50_BUFCTX_TEXTURES, res,
                                NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 
@@ -261,7 +285,7 @@ nv50_validate_tsc(struct nv50_context *nv50, int s)
       if (tsc->id < 0) {
          tsc->id = nv50_screen_tsc_alloc(nv50->screen, tsc);
 
-         nv50_sifc_linear_u8(&nv50->pipe, nv50->screen->txc,
+         nv50_sifc_linear_u8(&nv50->base, nv50->screen->txc,
                              65536 + tsc->id * 32,
                              NOUVEAU_BO_VRAM, 32, tsc->tsc);
          need_flush = TRUE;