radeonsi: Handle position input parameter for pixel shaders v2

[mesa.git] / src / gallium / drivers / nvc0 / nvc0_context.h

diff --git a/src/gallium/drivers/nvc0/nvc0_context.h b/src/gallium/drivers/nvc0/nvc0_context.h
index 8b80f2fe386d4f143b9c609a4c9c4b918a9c9b6c..ef792227b3436a7160545ffbd3fc58477db26451 100644 (file)
--- a/src/gallium/drivers/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nvc0/nvc0_context.h
@@ -10,7 +10,9 @@
 #include "util/u_inlines.h"
 #include "util/u_dynarray.h"
 
+#ifdef NVC0_WITH_DRAW_MODULE
 #include "draw/draw_vertex.h"
+#endif
 
 #include "nv50/nv50_debug.h"
 #include "nvc0_winsys.h"
@@ -27,7 +29,9 @@
 #include "nvc0_3d.xml.h"
 #include "nvc0_2d.xml.h"
 #include "nvc0_m2mf.xml.h"
+#include "nve4_p2mf.xml.h"
 
+/* NOTE: must keep NVC0_NEW_...PROG in consecutive bits in this order */
 #define NVC0_NEW_BLEND        (1 << 0)
 #define NVC0_NEW_RASTERIZER   (1 << 1)
 #define NVC0_NEW_ZSA          (1 << 2)
@@ -75,6 +79,11 @@ struct nvc0_context {
 
    struct nvc0_screen *screen;
 
+   void (*m2mf_copy_rect)(struct nvc0_context *,
+                          const struct nv50_m2mf_rect *dst,
+                          const struct nv50_m2mf_rect *src,
+                          uint32_t nblocksx, uint32_t nblocksy);
+
    uint32_t dirty;
 
    struct {
@@ -88,6 +97,7 @@ struct nvc0_context {
       uint32_t constant_elts;
       int32_t index_bias;
       uint16_t scissor;
+      uint8_t vbo_mode; /* 0 = normal, 1 = translate, 3 = translate, forced */
       uint8_t num_vtxbufs;
       uint8_t num_vtxelts;
       uint8_t num_textures[5];
@@ -111,17 +121,18 @@ struct nvc0_context {
    struct nvc0_program *gmtyprog;
    struct nvc0_program *fragprog;
 
-   struct pipe_resource *constbuf[5][16];
+   struct nvc0_constbuf constbuf[5][NVC0_MAX_PIPE_CONSTBUFS];
    uint16_t constbuf_dirty[5];
 
    struct pipe_vertex_buffer vtxbuf[PIPE_MAX_ATTRIBS];
    unsigned num_vtxbufs;
    struct pipe_index_buffer idxbuf;
    uint32_t constant_vbos;
-   uint32_t vbo_fifo; /* bitmask of vertex elements to be pushed to FIFO */
    uint32_t vbo_user; /* bitmask of vertex buffers pointing to user memory */
-   unsigned vbo_min_index; /* from pipe_draw_info, for vertex upload */
-   unsigned vbo_max_index;
+   uint32_t vb_elt_first; /* from pipe_draw_info, for vertex upload */
+   uint32_t vb_elt_limit; /* max - min element (count - 1) */
+   uint32_t instance_off; /* current base vertex for instanced arrays */
+   uint32_t instance_max; /* last instance for current draw call */
 
    struct pipe_sampler_view *textures[5][PIPE_MAX_SAMPLERS];
    unsigned num_textures[5];
@@ -130,6 +141,8 @@ struct nvc0_context {
    unsigned num_samplers[5];
    uint16_t samplers_dirty[5];
 
+   uint32_t tex_handles[5][PIPE_MAX_SAMPLERS]; /* for nve4 */
+
    struct pipe_framebuffer_state framebuffer;
    struct pipe_blend_color blend_colour;
    struct pipe_stencil_ref stencil_ref;
@@ -146,7 +159,9 @@ struct nvc0_context {
    struct pipe_stream_output_target *tfbbuf[4];
    unsigned num_tfbbufs;
 
+#ifdef NVC0_WITH_DRAW_MODULE
    struct draw_context *draw;
+#endif
 };
 
 static INLINE struct nvc0_context *
@@ -155,6 +170,23 @@ nvc0_context(struct pipe_context *pipe)
    return (struct nvc0_context *)pipe;
 }
 
+static INLINE unsigned
+nvc0_shader_stage(unsigned pipe)
+{
+   switch (pipe) {
+   case PIPE_SHADER_VERTEX: return 0;
+/* case PIPE_SHADER_TESSELLATION_CONTROL: return 1; */
+/* case PIPE_SHADER_TESSELLATION_EVALUATION: return 2; */
+   case PIPE_SHADER_GEOMETRY: return 3;
+   case PIPE_SHADER_FRAGMENT: return 4;
+   case PIPE_SHADER_COMPUTE: return 5;
+   default:
+      assert(!"invalid PIPE_SHADER type");
+      return 0;
+   }
+}
+
+
 /* nvc0_context.c */
 struct pipe_context *nvc0_create(struct pipe_screen *, void *);
 void nvc0_bufctx_fence(struct nvc0_context *, struct nouveau_bufctx *,
@@ -165,7 +197,7 @@ void nvc0_default_kick_notify(struct nouveau_pushbuf *);
 extern struct draw_stage *nvc0_draw_render_stage(struct nvc0_context *);
 
 /* nvc0_program.c */
-boolean nvc0_program_translate(struct nvc0_program *);
+boolean nvc0_program_translate(struct nvc0_program *, uint16_t chipset);
 boolean nvc0_program_upload_code(struct nvc0_context *, struct nvc0_program *);
 void nvc0_program_destroy(struct nvc0_context *, struct nvc0_program *);
 void nvc0_program_library_upload(struct nvc0_context *);
@@ -206,6 +238,7 @@ extern void nvc0_init_surface_functions(struct nvc0_context *);
 /* nvc0_tex.c */
 void nvc0_validate_textures(struct nvc0_context *);
 void nvc0_validate_samplers(struct nvc0_context *);
+void nve4_set_tex_handles(struct nvc0_context *);
 
 struct pipe_sampler_view *
 nvc0_create_sampler_view(struct pipe_context *,
@@ -214,19 +247,16 @@ nvc0_create_sampler_view(struct pipe_context *,
 
 /* nvc0_transfer.c */
 void
-nvc0_m2mf_transfer_rect(struct nvc0_context *,
-                        const struct nv50_m2mf_rect *dst,
-                        const struct nv50_m2mf_rect *src,
-                        uint32_t nblocksx, uint32_t nblocksy);
+nvc0_init_transfer_functions(struct nvc0_context *);
+
 void
 nvc0_m2mf_push_linear(struct nouveau_context *nv,
                       struct nouveau_bo *dst, unsigned offset, unsigned domain,
                       unsigned size, const void *data);
 void
-nvc0_m2mf_copy_linear(struct nouveau_context *nv,
-                     struct nouveau_bo *dst, unsigned dstoff, unsigned dstdom,
-                     struct nouveau_bo *src, unsigned srcoff, unsigned srcdom,
-                     unsigned size);
+nve4_p2mf_push_linear(struct nouveau_context *nv,
+                      struct nouveau_bo *dst, unsigned offset, unsigned domain,
+                      unsigned size, const void *data);
 void
 nvc0_cb_push(struct nouveau_context *,
              struct nouveau_bo *bo, unsigned domain,