radeon/llvm: Eliminate CFGStructurizer dependency on AMDIL instructions

[mesa.git] / src / gallium / drivers / nvc0 / nvc0_screen.h

diff --git a/src/gallium/drivers/nvc0/nvc0_screen.h b/src/gallium/drivers/nvc0/nvc0_screen.h
index 9abf4b1fd3dcd6e85a5887ff71b05cebb64ec178..69cddf2c9b0113794175152800ed730104c45f02 100644 (file)
--- a/src/gallium/drivers/nvc0/nvc0_screen.h
+++ b/src/gallium/drivers/nvc0/nvc0_screen.h
@@ -6,18 +6,18 @@
 #include "nouveau/nouveau_fence.h"
 #include "nouveau/nouveau_heap.h"
 
+#include "nouveau/nv_object.xml.h"
+
 #include "nvc0_winsys.h"
 #include "nvc0_stateobj.h"
 
 #define NVC0_TIC_MAX_ENTRIES 2048
 #define NVC0_TSC_MAX_ENTRIES 2048
 
-struct nvc0_context;
-
-#define NVC0_SCRATCH_SIZE (2 << 20)
-#define NVC0_SCRATCH_NR_BUFFERS 2
+/* doesn't count reserved slots (for auxiliary constants, immediates, etc.) */
+#define NVC0_MAX_PIPE_CONSTBUFS 14
 
-#define NVC0_SCREEN_RESIDENT_BO_COUNT 5
+struct nvc0_context;
 
 struct nvc0_blitctx;
 
@@ -29,10 +29,10 @@ struct nvc0_screen {
    int num_occlusion_queries_active;
 
    struct nouveau_bo *text;
-   struct nouveau_bo *uniforms;
+   struct nouveau_bo *uniform_bo;
    struct nouveau_bo *tls;
    struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
-   struct nouveau_bo *vfetch_cache;
+   struct nouveau_bo *poly_cache;
 
    uint64_t tls_size;
 
@@ -41,13 +41,6 @@ struct nvc0_screen {
 
    struct nvc0_blitctx *blitctx;
 
-   struct {
-      struct nouveau_bo *bo[NVC0_SCRATCH_NR_BUFFERS];
-      uint8_t *buf;
-      int index;
-      uint32_t offset;
-   } scratch;
-
    struct {
       void **entries;
       int next;
@@ -67,7 +60,7 @@ struct nvc0_screen {
 
    struct nouveau_mman *mm_VRAM_fe0;
 
-   struct nouveau_object *fermi;
+   struct nouveau_object *eng3d; /* sqrt(1/2)|kepler> + sqrt(1/2)|fermi> */
    struct nouveau_object *eng2d;
    struct nouveau_object *m2mf;
    struct nouveau_object *dijkstra;