memset(hw, 0, sizeof(uint32_t) * 4);
if (insn.op == NVFX_FP_OP_OPCODE_KIL)
- fp->fp_control |= NV34TCL_FP_CONTROL_USES_KIL;
+ fp->fp_control |= NV30_3D_FP_CONTROL_USES_KIL;
hw[0] |= (insn.op << NVFX_FP_OP_OPCODE_SHIFT);
hw[0] |= (insn.mask << NVFX_FP_OP_OUTMASK_SHIFT);
hw[2] |= (insn.scale << NVFX_FP_OP_DST_SCALE_SHIFT);
src.swz[1] = fsrc->Register.SwizzleY;
src.swz[2] = fsrc->Register.SwizzleZ;
src.swz[3] = fsrc->Register.SwizzleW;
+ src.indirect = 0;
+ src.indirect_reg = 0;
+ src.indirect_swz = 0;
return src;
}
{
const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
struct nvfx_insn insn;
- struct nvfx_src src[3], tmp, tmp2;
+ struct nvfx_src src[3], tmp;
struct nvfx_reg dst;
int mask, sat, unit = 0;
int ai = -1, ci = -1, ii = -1;
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
- if (ai == -1 || ai == fsrc->Register.Index) {
+ if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG && (0
+ || fsrc->Register.SwizzleX == PIPE_SWIZZLE_ALPHA
+ || fsrc->Register.SwizzleY == PIPE_SWIZZLE_ALPHA
+ || fsrc->Register.SwizzleZ == PIPE_SWIZZLE_ALPHA
+ || fsrc->Register.SwizzleW == PIPE_SWIZZLE_ALPHA
+ )) {
+ /* hardware puts 0 in fogcoord.w, but GL/Gallium want 1 there */
+ struct nvfx_src addend = nvfx_src(nvfx_fp_imm(fpc, 0, 0, 0, 1));
+ addend.swz[0] = fsrc->Register.SwizzleX;
+ addend.swz[1] = fsrc->Register.SwizzleY;
+ addend.swz[2] = fsrc->Register.SwizzleZ;
+ addend.swz[3] = fsrc->Register.SwizzleW;
+ src[i] = nvfx_src(temp(fpc));
+ nvfx_fp_emit(fpc, arith(0, ADD, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), addend, none));
+ } else if (ai == -1 || ai == fsrc->Register.Index) {
ai = fsrc->Register.Index;
src[i] = tgsi_src(fpc, fsrc);
} else {
case TGSI_OPCODE_IF:
// MOVRC0 R31 (TR0.xyzw), R<src>:
// IF (NE.xxxx) ELSE <else> END <end>
- if(!nvfx->is_nv4x)
+ if(!nvfx->use_nv4x)
goto nv3x_cflow;
nv40_fp_if(fpc, src[0]);
break;
case TGSI_OPCODE_ELSE:
{
uint32_t *hw;
- if(!nvfx->is_nv4x)
+ if(!nvfx->use_nv4x)
goto nv3x_cflow;
assert(util_dynarray_contains(&fpc->if_stack, unsigned));
hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)];
case TGSI_OPCODE_ENDIF:
{
uint32_t *hw;
- if(!nvfx->is_nv4x)
+ if(!nvfx->use_nv4x)
goto nv3x_cflow;
assert(util_dynarray_contains(&fpc->if_stack, unsigned));
hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)];
break;
case TGSI_OPCODE_CAL:
- if(!nvfx->is_nv4x)
+ if(!nvfx->use_nv4x)
goto nv3x_cflow;
nv40_fp_cal(fpc, finst->Label.Label);
break;
case TGSI_OPCODE_RET:
- if(!nvfx->is_nv4x)
+ if(!nvfx->use_nv4x)
goto nv3x_cflow;
nv40_fp_ret(fpc);
break;
case TGSI_OPCODE_BGNLOOP:
- if(!nvfx->is_nv4x)
+ if(!nvfx->use_nv4x)
goto nv3x_cflow;
/* TODO: we should support using two nested REPs to allow a > 255 iteration count */
nv40_fp_rep(fpc, 255, finst->Label.Label);
break;
case TGSI_OPCODE_BRK:
- if(!nvfx->is_nv4x)
+ if(!nvfx->use_nv4x)
goto nv3x_cflow;
nv40_fp_brk(fpc);
break;
case 2: hw = 3; break;
case 3: hw = 4; break;
}
- if(hw > ((nvfx->is_nv4x) ? 4 : 2)) {
+ if(hw > ((nvfx->use_nv4x) ? 4 : 2)) {
NOUVEAU_ERR("bad rcol index\n");
return FALSE;
}
struct tgsi_parse_context p;
int high_temp = -1, i;
struct util_semantic_set set;
- unsigned num_texcoords = nvfx->is_nv4x ? 10 : 8;
+ unsigned num_texcoords = nvfx->use_nv4x ? 10 : 8;
fpc->fp->num_slots = util_semantic_set_from_program_file(&set, fpc->pfp->pipe.tokens, TGSI_FILE_INPUT);
if(fpc->fp->num_slots > num_texcoords)
if (!fpc)
goto out_err;
- fpc->max_temps = nvfx->is_nv4x ? 48 : 32;
+ fpc->max_temps = nvfx->use_nv4x ? 48 : 32;
fpc->pfp = pfp;
fpc->fp = fp;
fpc->num_regs = 2;
for (unsigned i = 0; i < pfp->info.num_properties; ++i) {
if (pfp->info.properties[i].name == TGSI_PROPERTY_FS_COORD_ORIGIN) {
if(pfp->info.properties[i].data[0])
- fp->coord_conventions |= NV34TCL_COORD_CONVENTIONS_ORIGIN_INVERTED;
+ fp->coord_conventions |= NV30_3D_COORD_CONVENTIONS_ORIGIN_INVERTED;
} else if (pfp->info.properties[i].name == TGSI_PROPERTY_FS_COORD_PIXEL_CENTER) {
if(pfp->info.properties[i].data[0])
- fp->coord_conventions |= NV34TCL_COORD_CONVENTIONS_CENTER_INTEGER;
+ fp->coord_conventions |= NV30_3D_COORD_CONVENTIONS_CENTER_INTEGER;
}
}
if(!nvfx->is_nv4x)
fp->fp_control |= (fpc->num_regs-1)/2;
else
- fp->fp_control |= fpc->num_regs << NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT;
+ fp->fp_control |= fpc->num_regs << NV40_3D_FP_CONTROL_TEMP_COUNT__SHIFT;
/* Terminate final instruction */
if(fp->insn)
static inline void
nvfx_fp_memcpy(void* dst, const void* src, size_t len)
{
-#ifndef WORDS_BIGENDIAN
+#ifndef PIPE_ARCH_BIG_ENDIAN
memcpy(dst, src, len);
#else
size_t i;
for(i = 0; i < len; i += 4) {
- uint32_t v = (uint32_t*)((char*)src + i);
+ uint32_t v = *(uint32_t*)((char*)src + i);
*(uint32_t*)((char*)dst + i) = (v >> 16) | (v << 16);
}
#endif
nvfx_fragprog_validate(struct nvfx_context *nvfx)
{
struct nouveau_channel* chan = nvfx->screen->base.channel;
+ struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
struct nvfx_pipe_fragment_program *pfp = nvfx->fragprog;
struct nvfx_vertex_program* vp;
- /* Gallium always puts the point coord in GENERIC[0]
- * TODO: this is wrong, Gallium needs to be fixed
- */
- unsigned sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * (nvfx->rasterizer->pipe.sprite_coord_enable | 1);
+
+ // TODO: the multiplication by point_quad_rasterization is probably superfluous
+ unsigned sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
boolean emulate_sprite_flipping = sprite_coord_enable && nvfx->rasterizer->pipe.sprite_coord_mode;
unsigned key = emulate_sprite_flipping;
pfp->fps[key] = fp;
}
- vp = nvfx->render_mode == HW ? nvfx->vertprog : nvfx->swtnl.vertprog;
+ vp = nvfx->hw_vertprog;
if (fp->last_vp_id != vp->id || fp->last_sprite_coord_enable != sprite_coord_enable) {
int sprite_real_input = -1;
unsigned used_texcoords = 0;
for(unsigned i = 0; i < fp->num_slots; ++i) {
unsigned generic = fp->slot_to_generic[i];
- if(!((1 << generic) & sprite_coord_enable))
+ if((generic < 32) && !((1 << generic) & sprite_coord_enable))
{
unsigned char slot_mask = vp->generic_to_fp_input[generic];
if(slot_mask >= 0xf0)
for(i = 0; i < fp->num_slots; ++i) {
unsigned generic = fp->slot_to_generic[i];
- if((1 << generic) & sprite_coord_enable)
+ if((generic < 32) && ((1 << generic) & sprite_coord_enable))
{
if(fp->slot_to_fp_input[i] != sprite_reloc_input)
goto update_slots;
for(; i < fp->num_slots; ++i)
{
unsigned generic = fp->slot_to_generic[i];
- if((1 << generic) & sprite_coord_enable)
+ if((generic < 32) && ((1 << generic) & sprite_coord_enable))
fp->slot_to_fp_input[i] = sprite_reloc_input;
else
fp->slot_to_fp_input[i] = vp->generic_to_fp_input[generic] & 0xf;
nvfx->hw_fragprog = fp;
MARK_RING(chan, 8, 1);
- OUT_RING(chan, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1));
+ BEGIN_RING(chan, eng3d, NV30_3D_FP_ACTIVE_PROGRAM, 1);
OUT_RELOC(chan, fp->fpbo->bo, offset, NOUVEAU_BO_VRAM |
NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
- NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0,
- NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
- OUT_RING(chan, RING_3D(NV34TCL_FP_CONTROL, 1));
+ NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0,
+ NV30_3D_FP_ACTIVE_PROGRAM_DMA1);
+ BEGIN_RING(chan, eng3d, NV30_3D_FP_CONTROL, 1);
OUT_RING(chan, fp->fp_control);
if(!nvfx->is_nv4x) {
- OUT_RING(chan, RING_3D(NV34TCL_FP_REG_CONTROL, 1));
+ BEGIN_RING(chan, eng3d, NV30_3D_FP_REG_CONTROL, 1);
OUT_RING(chan, (1<<16)|0x4);
- OUT_RING(chan, RING_3D(NV34TCL_TX_UNITS_ENABLE, 1));
+ BEGIN_RING(chan, eng3d, NV30_3D_TEX_UNITS_ENABLE, 1);
OUT_RING(chan, fp->samplers);
}
}
unsigned pointsprite_control = fp->point_sprite_control | nvfx->rasterizer->pipe.point_quad_rasterization;
if(pointsprite_control != nvfx->hw_pointsprite_control)
{
- WAIT_RING(chan, 2);
- OUT_RING(chan, RING_3D(NV34TCL_POINT_SPRITE, 1));
+ BEGIN_RING(chan, eng3d, NV30_3D_POINT_SPRITE, 1);
OUT_RING(chan, pointsprite_control);
nvfx->hw_pointsprite_control = pointsprite_control;
}
unsigned fp_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; // TODO: GART?
fp_flags |= NOUVEAU_BO_DUMMY;
MARK_RING(chan, 2, 2);
- OUT_RELOC(chan, bo, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1), fp_flags, 0, 0);
+ OUT_RELOC(chan, bo, RING_3D(NV30_3D_FP_ACTIVE_PROGRAM, 1), fp_flags, 0, 0);
OUT_RELOC(chan, bo, offset, fp_flags | NOUVEAU_BO_LOW |
- NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0,
- NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
+ NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0,
+ NV30_3D_FP_ACTIVE_PROGRAM_DMA1);
nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGPROG;
}
struct nvfx_fragment_program_bo* next = fpbo->next;
nouveau_bo_unmap(fpbo->bo);
nouveau_bo_ref(0, &fpbo->bo);
- free(fpbo);
+ os_free_aligned(fpbo);
fpbo = next;
}
while(fpbo != fp->fpbo);
projects / mesa.git / blobdiff