#include "nvfx_resource.h"
#include "nouveau/nouveau_channel.h"
-#include "nouveau/nouveau_class.h"
+
#include "nouveau/nouveau_pushbuf.h"
static inline unsigned
}
- OUT_RING(chan, RING_3D(NV34TCL_VTXFMT(0), elements));
+ OUT_RING(chan, RING_3D(NV30_3D_VTXFMT(0), elements));
if(nvfx->use_vertex_buffers)
{
unsigned idx = 0;
idx = ve->idx;
}
- OUT_RING(chan, nvfx->vtxelt->vtxfmt[idx] | (vb->stride << NV34TCL_VTXFMT_STRIDE_SHIFT));
+ OUT_RING(chan, nvfx->vtxelt->vtxfmt[idx] | (vb->stride << NV30_3D_VTXFMT_STRIDE__SHIFT));
++idx;
}
if(idx != nvfx->vtxelt->num_elements)
OUT_RINGp(chan, nvfx->vtxelt->vtxfmt, nvfx->vtxelt->num_elements);
for(i = nvfx->vtxelt->num_elements; i < elements; ++i)
- OUT_RING(chan, NV34TCL_VTXFMT_TYPE_32_FLOAT);
+ OUT_RING(chan, NV30_3D_VTXFMT_TYPE_V32_FLOAT);
if(nvfx->is_nv4x) {
unsigned i;
}
}
- OUT_RING(chan, RING_3D(NV34TCL_VTXBUF_ADDRESS(0), elements));
+ OUT_RING(chan, RING_3D(NV30_3D_VTXBUF(0), elements));
if(nvfx->use_vertex_buffers)
{
unsigned idx = 0;
OUT_RELOC(chan, bo,
vb->buffer_offset + ve->src_offset + nvfx->base_vertex * vb->stride,
vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
- 0, NV34TCL_VTXBUF_ADDRESS_DMA1);
+ 0, NV30_3D_VTXBUF_DMA1);
++idx;
}
return TRUE;
}
+void
+nvfx_vbo_swtnl_validate(struct nvfx_context *nvfx)
+{
+ struct nouveau_channel* chan = nvfx->screen->base.channel;
+ unsigned num_outputs = nvfx->vertprog->draw_elements;
+ int elements = MAX2(num_outputs, nvfx->hw_vtxelt_nr);
+
+ if (!elements)
+ return;
+
+ WAIT_RING(chan, (1 + 6 + 1 + 2) + elements * 2);
+
+ OUT_RING(chan, RING_3D(NV30_3D_VTXFMT(0), elements));
+ for(unsigned i = 0; i < num_outputs; ++i)
+ OUT_RING(chan, (4 << NV30_3D_VTXFMT_SIZE__SHIFT) | NV30_3D_VTXFMT_TYPE_V32_FLOAT);
+ for(unsigned i = num_outputs; i < elements; ++i)
+ OUT_RING(chan, NV30_3D_VTXFMT_TYPE_V32_FLOAT);
+
+ if(nvfx->is_nv4x) {
+ unsigned i;
+ /* seems to be some kind of cache flushing */
+ for(i = 0; i < 3; ++i) {
+ OUT_RING(chan, RING_3D(0x1718, 1));
+ OUT_RING(chan, 0);
+ }
+ }
+
+ OUT_RING(chan, RING_3D(NV30_3D_VTXBUF(0), elements));
+ for (unsigned i = 0; i < elements; i++)
+ OUT_RING(chan, 0);
+
+ OUT_RING(chan, RING_3D(0x1710, 1));
+ OUT_RING(chan, 0);
+
+ nvfx->hw_vtxelt_nr = num_outputs;
+ nvfx->relocs_needed &=~ NVFX_RELOCATE_VTXBUF;
+}
+
void
nvfx_vbo_relocate(struct nvfx_context *nvfx)
{
struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->vertex_buffer_index];
struct nouveau_bo* bo = nvfx_resource(vb->buffer)->bo;
- OUT_RELOC(chan, bo, RING_3D(NV34TCL_VTXBUF_ADDRESS(ve->idx), 1),
+ OUT_RELOC(chan, bo, RING_3D(NV30_3D_VTXBUF(ve->idx), 1),
vb_flags, 0, 0);
OUT_RELOC(chan, bo, vb->buffer_offset + ve->src_offset + nvfx->base_vertex * vb->stride,
vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
- 0, NV34TCL_VTXBUF_ADDRESS_DMA1);
+ 0, NV30_3D_VTXBUF_DMA1);
}
nvfx->relocs_needed &=~ NVFX_RELOCATE_VTXBUF;
}
nvfx_idxbuf_emit(struct nvfx_context* nvfx, unsigned ib_flags)
{
struct nouveau_channel* chan = nvfx->screen->base.channel;
- unsigned ib_format = (nvfx->idxbuf.index_size == 2) ? NV34TCL_IDXBUF_FORMAT_TYPE_U16 : NV34TCL_IDXBUF_FORMAT_TYPE_U32;
+ unsigned ib_format = (nvfx->idxbuf.index_size == 2) ? NV30_3D_IDXBUF_FORMAT_TYPE_U16 : NV30_3D_IDXBUF_FORMAT_TYPE_U32;
struct nouveau_bo* bo = nvfx_resource(nvfx->idxbuf.buffer)->bo;
ib_flags |= nvfx->screen->index_buffer_reloc_flags | NOUVEAU_BO_RD;
MARK_RING(chan, 3, 3);
if(ib_flags & NOUVEAU_BO_DUMMY)
- OUT_RELOC(chan, bo, RING_3D(NV34TCL_IDXBUF_ADDRESS, 2), ib_flags, 0, 0);
+ OUT_RELOC(chan, bo, RING_3D(NV30_3D_IDXBUF_OFFSET, 2), ib_flags, 0, 0);
else
- OUT_RING(chan, RING_3D(NV34TCL_IDXBUF_ADDRESS, 2));
+ OUT_RING(chan, RING_3D(NV30_3D_IDXBUF_OFFSET, 2));
OUT_RELOC(chan, bo, nvfx->idxbuf.offset + 1, ib_flags | NOUVEAU_BO_LOW, 0, 0);
OUT_RELOC(chan, bo, ib_format, ib_flags | NOUVEAU_BO_OR,
- 0, NV34TCL_IDXBUF_FORMAT_DMA1);
+ 0, NV30_3D_IDXBUF_FORMAT_DMA1);
nvfx->relocs_needed &=~ NVFX_RELOCATE_IDXBUF;
}
unsigned nvfx_vertex_formats[PIPE_FORMAT_COUNT] =
{
- [PIPE_FORMAT_R32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT,
- [PIPE_FORMAT_R32G32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT,
- [PIPE_FORMAT_R32G32B32A32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT,
- [PIPE_FORMAT_R32G32B32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT,
- [PIPE_FORMAT_R16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT,
- [PIPE_FORMAT_R16G16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT,
- [PIPE_FORMAT_R16G16B16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT,
- [PIPE_FORMAT_R16G16B16A16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT,
- [PIPE_FORMAT_R8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM,
- [PIPE_FORMAT_R8G8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM,
- [PIPE_FORMAT_R8G8B8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM,
- [PIPE_FORMAT_R8G8B8A8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM,
- [PIPE_FORMAT_R8G8B8A8_USCALED] = NV34TCL_VTXFMT_TYPE_8_USCALED,
- [PIPE_FORMAT_R16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM,
- [PIPE_FORMAT_R16G16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM,
- [PIPE_FORMAT_R16G16B16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM,
- [PIPE_FORMAT_R16G16B16A16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM,
- [PIPE_FORMAT_R16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED,
- [PIPE_FORMAT_R16G16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED,
- [PIPE_FORMAT_R16G16B16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED,
- [PIPE_FORMAT_R16G16B16A16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED,
+ [PIPE_FORMAT_R32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT,
+ [PIPE_FORMAT_R32G32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT,
+ [PIPE_FORMAT_R32G32B32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT,
+ [PIPE_FORMAT_R32G32B32A32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT,
+ [PIPE_FORMAT_R16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT,
+ [PIPE_FORMAT_R16G16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT,
+ [PIPE_FORMAT_R16G16B16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT,
+ [PIPE_FORMAT_R16G16B16A16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT,
+ [PIPE_FORMAT_R8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM,
+ [PIPE_FORMAT_R8G8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM,
+ [PIPE_FORMAT_R8G8B8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM,
+ [PIPE_FORMAT_R8G8B8A8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM,
+ [PIPE_FORMAT_R8G8B8A8_USCALED] = NV30_3D_VTXFMT_TYPE_U8_USCALED,
+ [PIPE_FORMAT_R16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM,
+ [PIPE_FORMAT_R16G16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM,
+ [PIPE_FORMAT_R16G16B16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM,
+ [PIPE_FORMAT_R16G16B16A16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM,
+ [PIPE_FORMAT_R16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED,
+ [PIPE_FORMAT_R16G16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED,
+ [PIPE_FORMAT_R16G16B16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED,
+ [PIPE_FORMAT_R16G16B16A16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED,
};
static void *
if(ve->instance_divisor)
{
struct nvfx_low_frequency_element* lfve;
- cso->vtxfmt[i] = NV34TCL_VTXFMT_TYPE_32_FLOAT;
+ cso->vtxfmt[i] = NV30_3D_VTXFMT_TYPE_V32_FLOAT;
//if(ve->frequency == PIPE_ELEMENT_FREQUENCY_CONSTANT)
if(0)
if(type)
{
transkey.element[idx].output_format = ve->src_format;
- cso->vtxfmt[i] = (ncomp << NV34TCL_VTXFMT_SIZE_SHIFT) | type;
+ cso->vtxfmt[i] = (ncomp << NV30_3D_VTXFMT_SIZE__SHIFT) | type;
}
else
{
unsigned float32[4] = {PIPE_FORMAT_R32_FLOAT, PIPE_FORMAT_R32G32_FLOAT, PIPE_FORMAT_R32G32B32_FLOAT, PIPE_FORMAT_R32G32B32A32_FLOAT};
transkey.element[idx].output_format = float32[ncomp - 1];
cso->needs_translate = TRUE;
- cso->vtxfmt[i] = (ncomp << NV34TCL_VTXFMT_SIZE_SHIFT) | NV34TCL_VTXFMT_TYPE_32_FLOAT;
+ cso->vtxfmt[i] = (ncomp << NV30_3D_VTXFMT_SIZE__SHIFT) | NV30_3D_VTXFMT_TYPE_V32_FLOAT;
}
transkey.element[idx].output_offset = transkey.output_stride;
transkey.output_stride += (util_format_get_stride(transkey.element[idx].output_format, 1) + 3) & ~3;
cso->translate = translate_create(&transkey);
cso->vertex_length = transkey.output_stride >> 2;
- cso->max_vertices_per_packet = 2047 / cso->vertex_length;
+ cso->max_vertices_per_packet = 2047 / MAX2(cso->vertex_length, 1);
return (void *)cso;
}
projects / mesa.git / blobdiff