#include <stdint.h>
#include <stdbool.h>
+#include "panfrost-job.h"
#define MIDGARD_DBG_MSGS 0x0001
#define MIDGARD_DBG_SHADERS 0x0002
typedef enum {
midgard_alu_op_fadd = 0x10,
midgard_alu_op_fmul = 0x14,
+
midgard_alu_op_fmin = 0x28,
midgard_alu_op_fmax = 0x2C,
- midgard_alu_op_fmov = 0x30,
+
+ midgard_alu_op_fmov = 0x30, /* fmov_rte */
+ midgard_alu_op_fmov_rtz = 0x31,
+ midgard_alu_op_fmov_rtn = 0x32,
+ midgard_alu_op_fmov_rtp = 0x33,
midgard_alu_op_froundeven = 0x34,
midgard_alu_op_ftrunc = 0x35,
midgard_alu_op_ffloor = 0x36,
midgard_alu_op_fdot3r = 0x3D,
midgard_alu_op_fdot4 = 0x3E,
midgard_alu_op_freduce = 0x3F,
+
midgard_alu_op_iadd = 0x40,
midgard_alu_op_ishladd = 0x41,
midgard_alu_op_isub = 0x46,
+ midgard_alu_op_iaddsat = 0x48,
+ midgard_alu_op_uaddsat = 0x49,
+ midgard_alu_op_isubsat = 0x4E,
+ midgard_alu_op_usubsat = 0x4F,
+
midgard_alu_op_imul = 0x58,
+
midgard_alu_op_imin = 0x60,
midgard_alu_op_umin = 0x61,
midgard_alu_op_imax = 0x62,
midgard_alu_op_umax = 0x63,
+ midgard_alu_op_ihadd = 0x64,
+ midgard_alu_op_uhadd = 0x65,
+ midgard_alu_op_irhadd = 0x66,
+ midgard_alu_op_urhadd = 0x67,
midgard_alu_op_iasr = 0x68,
midgard_alu_op_ilsr = 0x69,
midgard_alu_op_ishl = 0x6E,
+
midgard_alu_op_iand = 0x70,
midgard_alu_op_ior = 0x71,
- midgard_alu_op_inot = 0x72,
- midgard_alu_op_iandnot = 0x74, /* (a, b) -> a & ~b, used for not/b2f */
+ midgard_alu_op_inand = 0x72, /* ~(a & b), for inot let a = b */
+ midgard_alu_op_inor = 0x73, /* ~(a | b) */
+ midgard_alu_op_iandnot = 0x74, /* (a & ~b), used for not/b2f */
+ midgard_alu_op_iornot = 0x75, /* (a | ~b) */
midgard_alu_op_ixor = 0x76,
- midgard_alu_op_ilzcnt = 0x78, /* Number of zeroes on left. 31 - ilzcnt(x) = findMSB(x) */
+ midgard_alu_op_inxor = 0x77, /* ~(a & b) */
+ midgard_alu_op_iclz = 0x78, /* Number of zeroes on left */
+ midgard_alu_op_ibitcount8 = 0x7A, /* Counts bits in 8-bit increments */
midgard_alu_op_imov = 0x7B,
- midgard_alu_op_iabs = 0x7C,
+ midgard_alu_op_iabsdiff = 0x7C,
+ midgard_alu_op_uabsdiff = 0x7D,
+ midgard_alu_op_ichoose = 0x7E, /* vector, component number - dupe for shuffle() */
+
midgard_alu_op_feq = 0x80,
midgard_alu_op_fne = 0x81,
midgard_alu_op_flt = 0x82,
midgard_alu_op_bball_eq = 0x89,
midgard_alu_op_fball_lt = 0x8A, /* all(lessThan(.., ..)) */
midgard_alu_op_fball_lte = 0x8B, /* all(lessThanEqual(.., ..)) */
+
midgard_alu_op_bbany_neq = 0x90, /* used for bvec4(1) */
midgard_alu_op_fbany_neq = 0x91, /* bvec4(0) also */
midgard_alu_op_fbany_lt = 0x92, /* any(lessThan(.., ..)) */
midgard_alu_op_fbany_lte = 0x93, /* any(lessThanEqual(.., ..)) */
- midgard_alu_op_f2i = 0x99,
- midgard_alu_op_f2u8 = 0x9C,
- midgard_alu_op_f2u = 0x9D,
+
+ midgard_alu_op_f2i_rte = 0x98,
+ midgard_alu_op_f2i_rtz = 0x99,
+ midgard_alu_op_f2i_rtn = 0x9A,
+ midgard_alu_op_f2i_rtp = 0x9B,
+ midgard_alu_op_f2u_rte = 0x9C,
+ midgard_alu_op_f2u_rtz = 0x9D,
+ midgard_alu_op_f2u_rtn = 0x9E,
+ midgard_alu_op_f2u_rtp = 0x9F,
midgard_alu_op_ieq = 0xA0,
midgard_alu_op_ine = 0xA1,
midgard_alu_op_ilt = 0xA4,
midgard_alu_op_ile = 0xA5,
midgard_alu_op_iball_eq = 0xA8,
- midgard_alu_op_ball = 0xA9,
+ midgard_alu_op_iball_neq = 0xA9,
midgard_alu_op_uball_lt = 0xAA,
midgard_alu_op_uball_lte = 0xAB,
midgard_alu_op_iball_lt = 0xAC,
midgard_alu_op_iball_lte = 0xAD,
+
midgard_alu_op_ibany_eq = 0xB0,
midgard_alu_op_ibany_neq = 0xB1,
midgard_alu_op_ubany_lt = 0xB2,
midgard_alu_op_ubany_lte = 0xB3,
midgard_alu_op_ibany_lt = 0xB4, /* any(lessThan(.., ..)) */
midgard_alu_op_ibany_lte = 0xB5, /* any(lessThanEqual(.., ..)) */
- midgard_alu_op_i2f = 0xB8,
- midgard_alu_op_u2f = 0xBC,
- midgard_alu_op_icsel = 0xC1,
- midgard_alu_op_fcsel_i = 0xC4,
+ midgard_alu_op_i2f_rte = 0xB8,
+ midgard_alu_op_i2f_rtz = 0xB9,
+ midgard_alu_op_i2f_rtn = 0xBA,
+ midgard_alu_op_i2f_rtp = 0xBB,
+ midgard_alu_op_u2f_rte = 0xBC,
+ midgard_alu_op_u2f_rtz = 0xBD,
+ midgard_alu_op_u2f_rtn = 0xBE,
+ midgard_alu_op_u2f_rtp = 0xBF,
+
+ midgard_alu_op_icsel_v = 0xC0, /* condition code r31 */
+ midgard_alu_op_icsel = 0xC1, /* condition code r31.w */
+ midgard_alu_op_fcsel_v = 0xC4,
midgard_alu_op_fcsel = 0xC5,
midgard_alu_op_fround = 0xC6,
+
midgard_alu_op_fatan_pt2 = 0xE8,
midgard_alu_op_fpow_pt1 = 0xEC,
+ midgard_alu_op_fpown_pt1 = 0xED,
+ midgard_alu_op_fpowr_pt1 = 0xEE,
+
midgard_alu_op_frcp = 0xF0,
midgard_alu_op_frsqrt = 0xF2,
midgard_alu_op_fsqrt = 0xF3,
typedef enum {
midgard_outmod_none = 0,
midgard_outmod_pos = 1,
- midgard_outmod_int = 2,
+ /* 0x2 unknown */
midgard_outmod_sat = 3
-} midgard_outmod;
+} midgard_outmod_float;
+
+typedef enum {
+ midgard_outmod_int_saturate = 0,
+ midgard_outmod_uint_saturate = 1,
+ midgard_outmod_int_wrap = 2,
+ midgard_outmod_int_high = 3, /* Overflowed portion */
+} midgard_outmod_int;
typedef enum {
- midgard_reg_mode_quarter = 0,
- midgard_reg_mode_half = 1,
- midgard_reg_mode_full = 2,
- midgard_reg_mode_double = 3 /* TODO: verify */
+ midgard_reg_mode_8 = 0,
+ midgard_reg_mode_16 = 1,
+ midgard_reg_mode_32 = 2,
+ midgard_reg_mode_64 = 3
} midgard_reg_mode;
typedef enum {
midgard_dest_override_none = 2
} midgard_dest_override;
+typedef enum {
+ midgard_int_sign_extend = 0,
+ midgard_int_zero_extend = 1,
+ midgard_int_normal = 2,
+ midgard_int_shift = 3
+} midgard_int_mod;
+
+#define MIDGARD_FLOAT_MOD_ABS (1 << 0)
+#define MIDGARD_FLOAT_MOD_NEG (1 << 1)
+
typedef struct
__attribute__((__packed__))
{
- bool abs : 1;
- bool negate : 1;
+ /* Either midgard_int_mod or from midgard_float_mod_*, depending on the
+ * type of op */
+ unsigned mod : 2;
/* replicate lower half if dest = half, or low/high half selection if
* dest = full
unsigned src1 : 13;
unsigned src2 : 13;
midgard_dest_override dest_override : 2;
- midgard_outmod outmod : 2;
+ midgard_outmod_float outmod : 2;
unsigned mask : 8;
}
midgard_vector_alu;
unsigned src1 : 6;
unsigned src2 : 11;
unsigned unknown : 1;
- midgard_outmod outmod : 2;
+ unsigned outmod : 2;
bool output_full : 1;
unsigned output_component : 3;
}
/* Unclear why this is on the L/S unit, but (with an address of 0,
* appropriate swizzle, magic constant 0x24, and xy mask?) moves fp32 cube
* map coordinates in r27 to its cube map texture coordinate
- * destination (e.g r29). 0x4 magic for loading from fp16 instead */
-
- midgard_op_store_cubemap_coords = 0x0E,
-
- midgard_op_load_attr_16 = 0x95,
- midgard_op_load_attr_32 = 0x94,
- midgard_op_load_vary_16 = 0x99,
- midgard_op_load_vary_32 = 0x98,
- midgard_op_load_color_buffer_16 = 0x9D,
- midgard_op_load_color_buffer_8 = 0xBA,
- midgard_op_load_uniform_16 = 0xAC,
- midgard_op_load_uniform_32 = 0xB0,
- midgard_op_store_vary_16 = 0xD5,
- midgard_op_store_vary_32 = 0xD4
+ * destination (e.g r29). 0x4 magic for lding from fp16 instead */
+
+ midgard_op_st_cubemap_coords = 0x0E,
+
+ /* Used in OpenCL. Probably can ld other things as well */
+ midgard_op_ld_global_id = 0x10,
+
+ /* The L/S unit can do perspective division a clock faster than the ALU
+ * if you're lucky. Put the vec4 in r27, and call with 0x24 as the
+ * unknown state; the output will be <x/w, y/w, z/w, 1>. Replace w with
+ * z for the z version */
+ midgard_op_ldst_perspective_division_z = 0x12,
+ midgard_op_ldst_perspective_division_w = 0x13,
+
+ /* val in r27.y, address embedded, outputs result to argument. Invert val for sub. Let val = +-1 for inc/dec. */
+ midgard_op_atomic_add = 0x40,
+ midgard_op_atomic_and = 0x44,
+ midgard_op_atomic_or = 0x48,
+ midgard_op_atomic_xor = 0x4C,
+
+ midgard_op_atomic_imin = 0x50,
+ midgard_op_atomic_umin = 0x54,
+ midgard_op_atomic_imax = 0x58,
+ midgard_op_atomic_umax = 0x5C,
+
+ midgard_op_atomic_xchg = 0x60,
+
+ /* Used for compute shader's __global arguments, __local variables (or
+ * for register spilling) */
+
+ midgard_op_ld_char = 0x81,
+ midgard_op_ld_char2 = 0x84,
+ midgard_op_ld_short = 0x85,
+ midgard_op_ld_char4 = 0x88, /* short2, int, float */
+ midgard_op_ld_short4 = 0x8C, /* int2, float2, long */
+ midgard_op_ld_int4 = 0x90, /* float4, long2 */
+
+ midgard_op_ld_attr_32 = 0x94,
+ midgard_op_ld_attr_16 = 0x95,
+ midgard_op_ld_attr_32i = 0x97,
+ midgard_op_ld_vary_32 = 0x98,
+ midgard_op_ld_vary_16 = 0x99,
+ midgard_op_ld_vary_32i = 0x9B,
+ midgard_op_ld_color_buffer_16 = 0x9D,
+
+ midgard_op_ld_uniform_16 = 0xAC,
+
+ midgard_op_ld_uniform_32 = 0xB0,
+ midgard_op_ld_color_buffer_8 = 0xBA,
+
+ midgard_op_st_char = 0xC0,
+ midgard_op_st_char2 = 0xC4, /* short */
+ midgard_op_st_char4 = 0xC8, /* short2, int, float */
+ midgard_op_st_short4 = 0xCC, /* int2, float2, long */
+ midgard_op_st_int4 = 0xD0, /* float4, long2 */
+
+ midgard_op_st_vary_32 = 0xD4,
+ midgard_op_st_vary_16 = 0xD5,
+ midgard_op_st_vary_32i = 0xD7,
+
+ /* Value to st in r27, location r26.w as short2 */
+ midgard_op_st_image_f = 0xD8,
+ midgard_op_st_image_ui = 0xDA,
+ midgard_op_st_image_i = 0xDB,
} midgard_load_store_op;
typedef enum {
midgard_interp_default = 2
} midgard_interpolation;
+typedef enum {
+ midgard_varying_mod_none = 0,
+
+ /* Other values unknown */
+
+ /* Take the would-be result and divide all components by its z/w
+ * (perspective division baked in with the load) */
+ midgard_varying_mod_perspective_z = 2,
+ midgard_varying_mod_perspective_w = 3,
+} midgard_varying_modifier;
+
typedef struct
__attribute__((__packed__))
{
- unsigned zero1 : 4; /* Always zero */
+ unsigned zero0 : 1; /* Always zero */
+
+ midgard_varying_modifier modifier : 2;
+
+ unsigned zero1: 1; /* Always zero */
/* Varying qualifiers, zero if not a varying */
unsigned flat : 1;
}
midgard_load_store;
+/* 8-bit register selector used in texture ops to select a bias/LOD/gradient
+ * register, shoved into the `bias` field */
+
+typedef struct
+__attribute__((__packed__))
+{
+ /* Combines with component_hi to form 2-bit component select out of
+ * xyzw, as the component for bias/LOD and the starting component of a
+ * gradient vector */
+
+ unsigned component_lo : 1;
+
+ /* Register select between r28/r29 */
+ unsigned select : 1;
+
+ /* For a half-register, selects the upper half */
+ unsigned upper : 1;
+
+ /* Specifies a full-register, clear for a half-register. Mutually
+ * exclusive with upper. */
+ unsigned full : 1;
+
+ /* Higher half of component_lo. Always seen to be set for LOD/bias
+ * and clear for processed gradients, but I'm not sure if that's a
+ * hardware requirement. */
+ unsigned component_hi : 1;
+
+ /* Padding to make this 8-bit */
+ unsigned zero : 3;
+} midgard_tex_register_select;
+
/* Texture pipeline results are in r28-r29 */
#define REG_TEX_BASE 28
/* Texture opcodes... maybe? */
-#define TEXTURE_OP_NORMAL 0x11
-#define TEXTURE_OP_TEXEL_FETCH 0x14
-
-/* Texture format types, found in format */
-#define TEXTURE_CUBE 0x00
-#define TEXTURE_2D 0x02
-#define TEXTURE_3D 0x03
+#define TEXTURE_OP_NORMAL 0x11 /* texture */
+#define TEXTURE_OP_LOD 0x12 /* textureLod */
+#define TEXTURE_OP_TEXEL_FETCH 0x14 /* texelFetch */
typedef struct
__attribute__((__packed__))
unsigned op : 6;
unsigned shadow : 1;
- unsigned unknown3 : 1;
+ unsigned is_gather : 1;
/* A little obscure, but last is set for the last texture operation in
* a shader. cont appears to just be last's opposite (?). Yeah, I know,
unsigned cont : 1;
unsigned last : 1;
- unsigned format : 5;
- unsigned has_offset : 1;
+ enum mali_texture_type format : 2;
+ unsigned zero : 2;
+
+ /* Is a register used to specify the
+ * LOD/bias/offset? If set, use the `bias` field as
+ * a register index. If clear, use the `bias` field
+ * as an immediate. */
+ unsigned lod_register : 1;
- /* Like in Bifrost */
- unsigned filter : 1;
+ /* Is a register used to specify an offset? If set, use the
+ * offset_reg_* fields to encode this, duplicated for each of the
+ * components. If clear, there is implcitly always an immediate offst
+ * specificed in offset_imm_* */
+ unsigned offset_register : 1;
+ unsigned in_reg_full : 1;
unsigned in_reg_select : 1;
unsigned in_reg_upper : 1;
+ unsigned in_reg_swizzle : 8;
- unsigned in_reg_swizzle_left : 2;
- unsigned in_reg_swizzle_right : 2;
-
- unsigned unknown1 : 2;
-
- unsigned unknown8 : 4;
+ unsigned unknown8 : 2;
unsigned out_full : 1;
unsigned unknownA : 4;
- unsigned offset_unknown1 : 1;
- unsigned offset_reg_select : 1;
- unsigned offset_reg_upper : 1;
- unsigned offset_unknown4 : 1;
- unsigned offset_unknown5 : 1;
- unsigned offset_unknown6 : 1;
- unsigned offset_unknown7 : 1;
- unsigned offset_unknown8 : 1;
- unsigned offset_unknown9 : 1;
-
- unsigned unknownB : 3;
-
- /* Texture bias or LOD, depending on whether it is executed in a
- * fragment/vertex shader respectively. Compute as int(2^8 * biasf).
+ /* In immediate mode, each offset field is an immediate range [0, 7].
+ *
+ * In register mode, offset_x becomes a register full / select / upper
+ * triplet and a vec3 swizzle is splattered across offset_y/offset_z in
+ * a genuinely bizarre way.
*
- * For texel fetch, this is the LOD as is. */
- unsigned bias : 8;
+ * For texel fetches in immediate mode, the range is the full [-8, 7],
+ * but for normal texturing the top bit must be zero and a register
+ * used instead. It's not clear where this limitation is from. */
+
+ signed offset_x : 4;
+ signed offset_y : 4;
+ signed offset_z : 4;
+
+ /* In immediate bias mode, for a normal texture op, this is
+ * texture bias, computed as int(2^8 * frac(biasf)), with
+ * bias_int = floor(bias). For a textureLod, it's that, but
+ * s/bias/lod. For a texel fetch, this is the LOD as-is.
+ *
+ * In register mode, this is a midgard_tex_register_select
+ * structure and bias_int is zero */
- unsigned unknown9 : 8;
+ unsigned bias : 8;
+ signed bias_int : 8;
unsigned texture_handle : 16;
unsigned sampler_handle : 16;
}
midgard_texture_word;
-/* Opcode name table */
-
-static char *alu_opcode_names[256] = {
- [midgard_alu_op_fadd] = "fadd",
- [midgard_alu_op_fmul] = "fmul",
- [midgard_alu_op_fmin] = "fmin",
- [midgard_alu_op_fmax] = "fmax",
- [midgard_alu_op_fmov] = "fmov",
- [midgard_alu_op_froundeven] = "froundeven",
- [midgard_alu_op_ftrunc] = "ftrunc",
- [midgard_alu_op_ffloor] = "ffloor",
- [midgard_alu_op_fceil] = "fceil",
- [midgard_alu_op_ffma] = "ffma",
- [midgard_alu_op_fdot3] = "fdot3",
- [midgard_alu_op_fdot3r] = "fdot3r",
- [midgard_alu_op_fdot4] = "fdot4",
- [midgard_alu_op_freduce] = "freduce",
- [midgard_alu_op_imin] = "imin",
- [midgard_alu_op_umin] = "umin",
- [midgard_alu_op_imax] = "imax",
- [midgard_alu_op_umax] = "umax",
- [midgard_alu_op_ishl] = "ishl",
- [midgard_alu_op_iasr] = "iasr",
- [midgard_alu_op_ilsr] = "ilsr",
- [midgard_alu_op_iadd] = "iadd",
- [midgard_alu_op_ishladd] = "ishladd",
- [midgard_alu_op_isub] = "isub",
- [midgard_alu_op_imul] = "imul",
- [midgard_alu_op_imov] = "imov",
- [midgard_alu_op_iabs] = "iabs",
- [midgard_alu_op_iand] = "iand",
- [midgard_alu_op_ior] = "ior",
- [midgard_alu_op_inot] = "inot",
- [midgard_alu_op_iandnot] = "iandnot",
- [midgard_alu_op_ixor] = "ixor",
- [midgard_alu_op_ilzcnt] = "ilzcnt",
- [midgard_alu_op_feq] = "feq",
- [midgard_alu_op_fne] = "fne",
- [midgard_alu_op_flt] = "flt",
- [midgard_alu_op_fle] = "fle",
- [midgard_alu_op_fball_eq] = "fball_eq",
- [midgard_alu_op_fbany_neq] = "fbany_neq",
- [midgard_alu_op_bball_eq] = "bball_eq",
- [midgard_alu_op_fball_lt] = "fball_lt",
- [midgard_alu_op_fball_lte] = "fball_lte",
- [midgard_alu_op_bbany_neq] = "bbany_neq",
- [midgard_alu_op_fbany_lt] = "fbany_lt",
- [midgard_alu_op_fbany_lte] = "fbany_lte",
- [midgard_alu_op_f2i] = "f2i",
- [midgard_alu_op_f2u] = "f2u",
- [midgard_alu_op_f2u8] = "f2u8",
- [midgard_alu_op_ieq] = "ieq",
- [midgard_alu_op_ine] = "ine",
- [midgard_alu_op_ult] = "ult",
- [midgard_alu_op_ule] = "ule",
- [midgard_alu_op_ilt] = "ilt",
- [midgard_alu_op_ile] = "ile",
- [midgard_alu_op_iball_eq] = "iball_eq",
- [midgard_alu_op_ball] = "ball",
- [midgard_alu_op_uball_lt] = "uball_lt",
- [midgard_alu_op_uball_lte] = "uball_lte",
- [midgard_alu_op_iball_lt] = "iball_lt",
- [midgard_alu_op_iball_lte] = "iball_lte",
- [midgard_alu_op_iball_eq] = "iball_eq",
- [midgard_alu_op_ibany_neq] = "ibany_neq",
- [midgard_alu_op_ubany_lt] = "ubany_lt",
- [midgard_alu_op_ubany_lte] = "ubany_lte",
- [midgard_alu_op_ibany_lt] = "ibany_lt",
- [midgard_alu_op_ibany_lte] = "ibany_lte",
- [midgard_alu_op_i2f] = "i2f",
- [midgard_alu_op_u2f] = "u2f",
- [midgard_alu_op_icsel] = "icsel",
- [midgard_alu_op_fcsel_i] = "fcsel_i",
- [midgard_alu_op_fcsel] = "fcsel",
- [midgard_alu_op_fround] = "fround",
- [midgard_alu_op_fatan_pt2] = "fatan_pt2",
- [midgard_alu_op_frcp] = "frcp",
- [midgard_alu_op_frsqrt] = "frsqrt",
- [midgard_alu_op_fsqrt] = "fsqrt",
- [midgard_alu_op_fpow_pt1] = "fpow_pt1",
- [midgard_alu_op_fexp2] = "fexp2",
- [midgard_alu_op_flog2] = "flog2",
- [midgard_alu_op_fsin] = "fsin",
- [midgard_alu_op_fcos] = "fcos",
- [midgard_alu_op_fatan2_pt1] = "fatan2_pt1"
-};
-
-static char *load_store_opcode_names[256] = {
- [midgard_op_store_cubemap_coords] = "st_cubemap_coords",
- [midgard_op_load_attr_16] = "ld_attr_16",
- [midgard_op_load_attr_32] = "ld_attr_32",
- [midgard_op_load_vary_16] = "ld_vary_16",
- [midgard_op_load_vary_32] = "ld_vary_32",
- [midgard_op_load_uniform_16] = "ld_uniform_16",
- [midgard_op_load_uniform_32] = "ld_uniform_32",
- [midgard_op_load_color_buffer_8] = "ld_color_buffer_8",
- [midgard_op_load_color_buffer_16] = "ld_color_buffer_16",
- [midgard_op_store_vary_16] = "st_vary_16",
- [midgard_op_store_vary_32] = "st_vary_32"
-};
-
#endif