panfrost/midgard: Identify the in_reg_full field

[mesa.git] / src / gallium / drivers / panfrost / midgard / midgard.h

diff --git a/src/gallium/drivers/panfrost/midgard/midgard.h b/src/gallium/drivers/panfrost/midgard/midgard.h
index 68e969ccf9c8265337925b60faf0c7b62a71c096..841f6e5241b04ff451c38684105f5360611819e7 100644 (file)
--- a/src/gallium/drivers/panfrost/midgard/midgard.h
+++ b/src/gallium/drivers/panfrost/midgard/midgard.h
@@ -371,6 +371,13 @@ typedef enum {
         /* Used in OpenCL. Probably can ld other things as well */
         midgard_op_ld_global_id = 0x10,
 
+        /* The L/S unit can do perspective division a clock faster than the ALU
+         * if you're lucky. Put the vec4 in r27, and call with 0x24 as the
+         * unknown state; the output will be <x/w, y/w, z/w, 1>. Replace w with
+         * z for the z version */
+        midgard_op_ldst_perspective_division_z = 0x12,
+        midgard_op_ldst_perspective_division_w = 0x13,
+
         /* val in r27.y, address embedded, outputs result to argument. Invert val for sub. Let val = +-1 for inc/dec. */
         midgard_op_atomic_add = 0x40,
         midgard_op_atomic_and = 0x44,
@@ -428,10 +435,25 @@ typedef enum {
         midgard_interp_default = 2
 } midgard_interpolation;
 
+typedef enum {
+        midgard_varying_mod_none = 0,
+
+        /* Other values unknown */
+
+        /* Take the would-be result and divide all components by its z/w
+         * (perspective division baked in with the load)  */
+        midgard_varying_mod_perspective_z = 2,
+        midgard_varying_mod_perspective_w = 3,
+} midgard_varying_modifier;
+
 typedef struct
 __attribute__((__packed__))
 {
-        unsigned zero1 : 4; /* Always zero */
+        unsigned zero0 : 1; /* Always zero */
+
+        midgard_varying_modifier modifier : 2;
+
+        unsigned zero1: 1; /* Always zero */
 
         /* Varying qualifiers, zero if not a varying */
         unsigned flat    : 1;
@@ -471,8 +493,9 @@ midgard_load_store;
 #define REG_TEX_BASE 28
 
 /* Texture opcodes... maybe? */
-#define TEXTURE_OP_NORMAL 0x11
-#define TEXTURE_OP_TEXEL_FETCH 0x14
+#define TEXTURE_OP_NORMAL 0x11          /* texture */
+#define TEXTURE_OP_LOD 0x12             /* textureLod */
+#define TEXTURE_OP_TEXEL_FETCH 0x14     /* texelFetch */
 
 /* Texture format types, found in format */
 #define TEXTURE_CUBE 0x00
@@ -497,7 +520,13 @@ __attribute__((__packed__))
         unsigned cont  : 1;
         unsigned last  : 1;
 
-        unsigned format    : 5;
+        unsigned format    : 4;
+
+        /* Is a register used to specify the
+         * LOD/bias/offset? If set, use the `bias` field as
+         * a register index. If clear, use the `bias` field
+         * as an immediate. */
+        unsigned lod_register : 1;
 
         /* Is a register used to specify an offset? If set, use the
          * offset_reg_* fields to encode this, duplicated for each of the
@@ -505,9 +534,7 @@ __attribute__((__packed__))
          * specificed in offset_imm_* */
         unsigned offset_register : 1;
 
-        /* Like in Bifrost */
-        unsigned filter  : 1;
-
+        unsigned in_reg_full  : 1;
         unsigned in_reg_select : 1;
         unsigned in_reg_upper  : 1;
         unsigned in_reg_swizzle : 8;
@@ -548,9 +575,8 @@ __attribute__((__packed__))
          * fragment/vertex shader respectively. Compute as int(2^8 * biasf).
          *
          * For texel fetch, this is the LOD as is. */
-        unsigned bias  : 8;
-
-        unsigned unknown9  : 8;
+        unsigned bias : 8;
+        unsigned bias_int  : 8;
 
         unsigned texture_handle : 16;
         unsigned sampler_handle : 16;