panfrost: Implement instanced rendering

[mesa.git] / src / gallium / drivers / panfrost / midgard / midgard_compile.c

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 9e6ba5d39cf0acee5181b8185c625df4f73fdc5e..5559aa4445491129a5ab6fbdfa9182dca06a7def 100644 (file)
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -1091,7 +1091,7 @@ emit_varying_read(
                 compiler_context *ctx,
                 unsigned dest, unsigned offset,
                 unsigned nr_comp, unsigned component,
-                nir_src *indirect_offset)
+                nir_src *indirect_offset, nir_alu_type type)
 {
         /* XXX: Half-floats? */
         /* TODO: swizzle, mask */
@@ -1119,6 +1119,23 @@ emit_varying_read(
                 ins.load_store.unknown = 0x1e9e; /* xxx: what is this? */
         }
 
+        /* Use the type appropriate load */
+        switch (type) {
+                case nir_type_uint:
+                case nir_type_bool:
+                        ins.load_store.op = midgard_op_ld_vary_32u;
+                        break;
+                case nir_type_int:
+                        ins.load_store.op = midgard_op_ld_vary_32i;
+                        break;
+                case nir_type_float:
+                        ins.load_store.op = midgard_op_ld_vary_32;
+                        break;
+                default:
+                        unreachable("Attempted to load unknown type");
+                        break;
+        }
+
         emit_mir_instruction(ctx, ins);
 }
 
@@ -1237,6 +1254,12 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
                 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
                 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
 
+                /* Get the base type of the intrinsic */
+                /* TODO: Infer type? Does it matter? */
+                nir_alu_type t =
+                        is_ubo ? nir_type_uint : nir_intrinsic_type(instr);
+                t = nir_alu_type_get_base_type(t);
+
                 if (!is_ubo) {
                         offset = nir_intrinsic_base(instr);
                 }
@@ -1276,7 +1299,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
                         uint32_t uindex = nir_src_as_uint(index) + 1;
                         emit_ubo_read(ctx, reg, offset / 16, NULL, uindex);
                 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
-                        emit_varying_read(ctx, reg, offset, nr_comp, component, !direct ? &instr->src[0] : NULL);
+                        emit_varying_read(ctx, reg, offset, nr_comp, component, !direct ? &instr->src[0] : NULL, t);
                 } else if (ctx->is_blend) {
                         /* For blend shaders, load the input color, which is
                          * preloaded to r0 */
@@ -1287,6 +1310,24 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
                         midgard_instruction ins = m_ld_attr_32(reg, offset);
                         ins.load_store.unknown = 0x1E1E; /* XXX: What is this? */
                         ins.load_store.mask = mask_of(nr_comp);
+
+                        /* Use the type appropriate load */
+                        switch (t) {
+                                case nir_type_uint:
+                                case nir_type_bool:
+                                        ins.load_store.op = midgard_op_ld_attr_32u;
+                                        break;
+                                case nir_type_int:
+                                        ins.load_store.op = midgard_op_ld_attr_32i;
+                                        break;
+                                case nir_type_float:
+                                        ins.load_store.op = midgard_op_ld_attr_32;
+                                        break;
+                                default:
+                                        unreachable("Attempted to load unknown type");
+                                        break;
+                        }
+
                         emit_mir_instruction(ctx, ins);
                 } else {
                         DBG("Unknown load\n");
@@ -1455,6 +1496,21 @@ pan_attach_constant_bias(
         return true;
 }
 
+static enum mali_sampler_type
+midgard_sampler_type(nir_alu_type t)
+{
+        switch (nir_alu_type_get_base_type(t)) {
+                case nir_type_float:
+                        return MALI_SAMPLER_FLOAT;
+                case nir_type_int:
+                        return MALI_SAMPLER_SIGNED;
+                case nir_type_uint:
+                        return MALI_SAMPLER_UNSIGNED;
+                default:
+                        unreachable("Unknown sampler type");
+        }
+}
+
 static void
 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
                  unsigned midgard_texop)
@@ -1492,8 +1548,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
                         .in_reg_full = 1,
                         .out_full = 1,
 
-                        /* Always 1 */
-                        .unknown7 = 1,
+                        .sampler_type = midgard_sampler_type(instr->dest_type),
                 }
         };
 
@@ -1555,7 +1610,8 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
                                         /* Non-texel fetch doesn't need that
                                          * nonsense. However we do use the Z
                                          * for array indexing */
-                                        ins.texture.in_reg_swizzle = SWIZZLE_XYXZ;
+                                        bool is_3d = instr->sampler_dim == GLSL_SAMPLER_DIM_3D;
+                                        ins.texture.in_reg_swizzle = is_3d ? SWIZZLE_XYZZ : SWIZZLE_XYXZ;
                                 }
                         }