panfrost/midgard: Apply code styling

[mesa.git] / src / gallium / drivers / panfrost / midgard / midgard_ra.c

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_ra.c b/src/gallium/drivers/panfrost/midgard/midgard_ra.c
index 77ec65b4eae9ad4b563d5f6166f14540f3c8f213..cfe091326ed13579b41b1c216ea273953ffe7087 100644 (file)
--- a/src/gallium/drivers/panfrost/midgard/midgard_ra.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_ra.c
@@ -49,8 +49,8 @@
 static unsigned reg_type_to_mask[WORK_STRIDE] = {
         0xF,                                    /* xyzw */
         0x7, 0x7 << 1,                          /* xyz */
-        0x3, 0x3 << 1, 0x3 << 2,                /* xy */
-        0x1, 0x1 << 1, 0x1 << 2, 0x1 << 3       /* x */
+                 0x3, 0x3 << 1, 0x3 << 2,                /* xy */
+                 0x1, 0x1 << 1, 0x1 << 2, 0x1 << 3       /* x */
 };
 
 static unsigned reg_type_to_swizzle[WORK_STRIDE] = {
@@ -92,14 +92,7 @@ static unsigned
 compose_swizzle(unsigned swizzle, unsigned mask,
                 struct phys_reg reg, struct phys_reg dst)
 {
-        unsigned out = 0;
-
-        for (unsigned c = 0; c < 4; ++c) {
-                unsigned s = (swizzle >> (2*c)) & 0x3;
-                unsigned q = (reg.swizzle >> (2*s)) & 0x3;
-
-                out |= (q << (2*c));
-        }
+        unsigned out = pan_compose_swizzle(swizzle, reg.swizzle);
 
         /* Based on the register mask, we need to adjust over. E.g if we're
          * writing to yz, a base swizzle of xy__ becomes _xy_. Save the
@@ -130,7 +123,7 @@ find_or_allocate_temp(compiler_context *ctx, unsigned hash)
                 return hash;
 
         unsigned temp = (uintptr_t) _mesa_hash_table_u64_search(
-                        ctx->hash_to_temp, hash + 1);
+                                ctx->hash_to_temp, hash + 1);
 
         if (temp)
                 return temp - 1;
@@ -140,7 +133,7 @@ find_or_allocate_temp(compiler_context *ctx, unsigned hash)
         ctx->max_hash = MAX2(ctx->max_hash, hash);
 
         _mesa_hash_table_u64_insert(ctx->hash_to_temp,
-                        hash + 1, (void *) ((uintptr_t) temp + 1));
+                                    hash + 1, (void *) ((uintptr_t) temp + 1));
 
         return temp;
 }
@@ -258,7 +251,7 @@ allocate_registers(compiler_context *ctx)
 
                                 if (mask1 & mask2)
                                         ra_add_reg_conflict(regs,
-                                                        base + a, base + b);
+                                                            base + a, base + b);
                         }
                 }
         }
@@ -300,16 +293,7 @@ allocate_registers(compiler_context *ctx)
                         if (ins->ssa_args.dest < 0) continue;
                         if (ins->ssa_args.dest >= SSA_FIXED_MINIMUM) continue;
 
-                        /* Default to vec4 if we're not sure */
-
-                        int mask = 0xF;
-
-                        if (ins->type == TAG_ALU_4)
-                                mask = squeeze_writemask(ins->alu.mask);
-                        else if (ins->type == TAG_LOAD_STORE_4)
-                                mask = ins->load_store.mask;
-
-                        int class = util_logbase2(mask) + 1;
+                        int class = util_logbase2(ins->mask) + 1;
 
                         /* Use the largest class if there's ambiguity, this
                          * handles partial writes */
@@ -424,9 +408,9 @@ allocate_registers(compiler_context *ctx)
 
 static void
 install_registers_instr(
-                compiler_context *ctx,
-                struct ra_graph *g,
-                midgard_instruction *ins)
+        compiler_context *ctx,
+        struct ra_graph *g,
+        midgard_instruction *ins)
 {
         ssa_args args = ins->ssa_args;
 
@@ -437,16 +421,16 @@ install_registers_instr(
                 struct phys_reg src2 = index_to_reg(ctx, g, adjusted_src);
                 struct phys_reg dest = index_to_reg(ctx, g, args.dest);
 
-                unsigned mask = squeeze_writemask(ins->alu.mask);
-                ins->alu.mask = expand_writemask(compose_writemask(mask, dest));
+                unsigned uncomposed_mask = ins->mask;
+                ins->mask = compose_writemask(uncomposed_mask, dest);
 
                 /* Adjust the dest mask if necessary. Mostly this is a no-op
                  * but it matters for dot products */
-                dest.mask = effective_writemask(&ins->alu);
+                dest.mask = effective_writemask(&ins->alu, ins->mask);
 
                 midgard_vector_alu_src mod1 =
                         vector_alu_from_unsigned(ins->alu.src1);
-                mod1.swizzle = compose_swizzle(mod1.swizzle, mask, src1, dest);
+                mod1.swizzle = compose_swizzle(mod1.swizzle, uncomposed_mask, src1, dest);
                 ins->alu.src1 = vector_alu_srco_unsigned(mod1);
 
                 ins->registers.src1_reg = src1.reg;
@@ -461,14 +445,14 @@ install_registers_instr(
 
                         int lower_11 = ins->inline_constant & ((1 << 12) - 1);
                         uint16_t imm = ((lower_11 >> 8) & 0x7) |
-                                ((lower_11 & 0xFF) << 3);
+                                       ((lower_11 & 0xFF) << 3);
 
                         ins->alu.src2 = imm << 2;
                 } else {
                         midgard_vector_alu_src mod2 =
                                 vector_alu_from_unsigned(ins->alu.src2);
                         mod2.swizzle = compose_swizzle(
-                                        mod2.swizzle, mask, src2, dest);
+                                               mod2.swizzle, uncomposed_mask, src2, dest);
                         ins->alu.src2 = vector_alu_srco_unsigned(mod2);
 
                         ins->registers.src2_reg = src2.reg;
@@ -488,17 +472,17 @@ install_registers_instr(
                          * logical dataflow */
 
                         unsigned r = OP_IS_STORE(ins->load_store.op) ?
-                                args.src0 : args.dest;
+                                     args.src0 : args.dest;
                         struct phys_reg src = index_to_reg(ctx, g, r);
 
                         ins->load_store.reg = src.reg;
 
                         ins->load_store.swizzle = compose_swizzle(
-                                        ins->load_store.swizzle, 0xF,
-                                        default_phys_reg(0), src);
+                                                          ins->load_store.swizzle, 0xF,
+                                                          default_phys_reg(0), src);
 
-                        ins->load_store.mask = compose_writemask(
-                                        ins->load_store.mask, src);
+                        ins->mask = compose_writemask(
+                                            ins->mask, src);
                 }
 
                 break;