struct pipe_blend_state *cso,
enum pipe_format format)
{
+ struct panfrost_screen *screen = pan_screen(ctx->base.screen);
struct panfrost_blend_shader res;
+ res.ctx = ctx;
+
/* Build the shader */
nir_shader *shader = nir_shader_create(NULL, MESA_SHADER_FRAGMENT, &midgard_nir_options, NULL);
nir_make_options(cso, 1);
NIR_PASS_V(shader, nir_lower_blend, options);
- NIR_PASS_V(shader, nir_lower_framebuffer, format);
+ NIR_PASS_V(shader, nir_lower_framebuffer, format, screen->gpu_id);
/* Compile the built shader */
midgard_program program;
- midgard_compile_shader_nir(shader, &program, true);
-
- /* Upload the shader */
-
- int size = program.compiled.size;
- uint8_t *dst = program.compiled.data;
-
- res.shader.cpu = mem_dup(dst, size);
- res.shader.gpu = panfrost_upload(&ctx->shaders, dst, size);
+ midgard_compile_shader_nir(shader, &program, true, screen->gpu_id);
/* At least two work registers are needed due to an encoding quirk */
res.work_count = MAX2(program.work_register_count, 2);
/* Allow us to patch later */
res.patch_index = program.blend_patch_offset;
res.first_tag = program.first_tag;
- res.size = size;
+ res.size = program.compiled.size;
+ res.buffer = program.compiled.data;
return res;
}