radeonsi/gfx10: update a tunable max_es_verts_base for NGG

[mesa.git] / src / gallium / drivers / panfrost / pan_blend_shaders.c

diff --git a/src/gallium/drivers/panfrost/pan_blend_shaders.c b/src/gallium/drivers/panfrost/pan_blend_shaders.c
index 993b612ee5041a4a72fec0b086c9cdba7cec3ee6..a58808ba7be3d1247deae358306e3079f52d1aa2 100644 (file)
--- a/src/gallium/drivers/panfrost/pan_blend_shaders.c
+++ b/src/gallium/drivers/panfrost/pan_blend_shaders.c
@@ -27,7 +27,7 @@
 #include "pan_util.h"
 #include "midgard/midgard_compile.h"
 #include "compiler/nir/nir_builder.h"
-#include "midgard/nir_lower_blend.h"
+#include "nir/nir_lower_blend.h"
 #include "gallium/auxiliary/util/u_blend.h"
 #include "util/u_memory.h"
 
@@ -127,9 +127,9 @@ nir_make_options(const struct pipe_blend_state *blend, unsigned nr_cbufs)
 
 struct panfrost_blend_shader
 panfrost_compile_blend_shader(
-                struct panfrost_context *ctx,
-                struct pipe_blend_state *cso,
-                enum pipe_format format)
+        struct panfrost_context *ctx,
+        struct pipe_blend_state *cso,
+        enum pipe_format format)
 {
         struct panfrost_blend_shader res;
 
@@ -178,7 +178,7 @@ panfrost_compile_blend_shader(
         uint8_t *dst = program.compiled.data;
 
         res.shader.cpu = mem_dup(dst, size);
-        res.shader.gpu = panfrost_upload(&ctx->shaders, dst, size, true);
+        res.shader.gpu = panfrost_upload(&ctx->shaders, dst, size);
 
         /* At least two work registers are needed due to an encoding quirk */
         res.work_count = MAX2(program.work_register_count, 2);