meta->sampler_count = ctx->sampler_count[st];
if (dev->quirks & IS_BIFROST) {
- meta->bifrost1.unk1 = 0x800200;
+ if (st == PIPE_SHADER_VERTEX)
+ meta->bifrost1.unk1 = 0x800000;
+ else {
+ /* First clause ATEST |= 0x4000000.
+ * Less than 32 regs |= 0x200 */
+ meta->bifrost1.unk1 = 0x958020;
+ }
+
meta->bifrost1.uniform_buffer_count = panfrost_ubo_count(ctx, st);
- meta->bifrost2.preload_regs = 0xC0;
+ if (st == PIPE_SHADER_VERTEX)
+ meta->bifrost2.preload_regs = 0xC0;
+ else
+ meta->bifrost2.preload_regs = 0x1;
meta->bifrost2.uniform_count = MIN2(ss->uniform_count,
ss->uniform_cutoff);
} else {
meta->midgard1.flags_lo = 0x220;
meta->midgard1.uniform_buffer_count = panfrost_ubo_count(ctx, st);
}
-
}
static unsigned
blend[c] = panfrost_get_blend_for_context(ctx, c, &shader_bo,
&shader_offset);
- /* If there is a blend shader, work registers are shared. XXX: opt */
+ /* If there is a blend shader, work registers are shared. We impose 8
+ * work registers as a limit for blend shaders. Should be lower XXX */
- for (unsigned c = 0; c < rt_count; ++c) {
- if (blend[c].is_shader)
- fragmeta->midgard1.work_count = 16;
+ if (!(dev->quirks & IS_BIFROST)) {
+ for (unsigned c = 0; c < rt_count; ++c) {
+ if (blend[c].is_shader) {
+ fragmeta->midgard1.work_count =
+ MAX2(fragmeta->midgard1.work_count, 8);
+ }
+ }
}
/* Even on MFBD, the shader descriptor gets blend shaders. It's *also*
SET_BIT(fragmeta->unknown2_4, 0x10, dev->quirks & MIDGARD_SFBD);
- /* Depending on whether it's legal to in the given shader, we try to
- * enable early-z testing (or forward-pixel kill?) */
+ if (dev->quirks & IS_BIFROST) {
+ /* TODO */
+ } else {
+ /* Depending on whether it's legal to in the given shader, we try to
+ * enable early-z testing (or forward-pixel kill?) */
+
+ SET_BIT(fragmeta->midgard1.flags_lo, MALI_EARLY_Z,
+ !fs->can_discard && !fs->writes_depth);
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_EARLY_Z,
- !fs->can_discard && !fs->writes_depth);
+ /* Add the writes Z/S flags if needed. */
+ SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_Z, fs->writes_depth);
+ SET_BIT(fragmeta->midgard1.flags_hi, MALI_WRITES_S, fs->writes_stencil);
- /* Add the writes Z/S flags if needed. */
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_Z, fs->writes_depth);
- SET_BIT(fragmeta->midgard1.flags_hi, MALI_WRITES_S, fs->writes_stencil);
+ /* Any time texturing is used, derivatives are implicitly calculated,
+ * so we need to enable helper invocations */
- /* Any time texturing is used, derivatives are implicitly calculated,
- * so we need to enable helper invocations */
+ SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS,
+ fs->helper_invocations);
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS,
- fs->helper_invocations);
+ /* CAN_DISCARD should be set if the fragment shader possibly contains a
+ * 'discard' instruction. It is likely this is related to optimizations
+ * related to forward-pixel kill, as per "Mali Performance 3: Is
+ * EGL_BUFFER_PRESERVED a good thing?" by Peter Harris */
- /* CAN_DISCARD should be set if the fragment shader possibly contains a
- * 'discard' instruction. It is likely this is related to optimizations
- * related to forward-pixel kill, as per "Mali Performance 3: Is
- * EGL_BUFFER_PRESERVED a good thing?" by Peter Harris */
+ const struct pipe_depth_stencil_alpha_state *zsa = ctx->depth_stencil;
- SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD, fs->can_discard);
- SET_BIT(fragmeta->midgard1.flags_lo, 0x400, fs->can_discard);
+ bool depth_enabled = fs->writes_depth ||
+ (zsa && zsa->depth.enabled && zsa->depth.func != PIPE_FUNC_ALWAYS);
+
+ SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD, fs->can_discard);
+ SET_BIT(fragmeta->midgard1.flags_lo, 0x400, !depth_enabled && fs->can_discard);
+ SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_ZS, depth_enabled && fs->can_discard);
+ }
panfrost_frag_meta_rasterizer_update(ctx, fragmeta);
panfrost_frag_meta_zsa_update(ctx, fragmeta);
struct pipe_sampler_view *pview = &view->base;
struct panfrost_resource *rsrc = pan_resource(pview->texture);
+ /* Add the BOs to the job so they are retained until the job is done. */
+
panfrost_batch_add_bo(batch, rsrc->bo,
PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ |
panfrost_bo_access_for_stage(stage));
+ panfrost_batch_add_bo(batch, view->bifrost_bo,
+ PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ |
+ panfrost_bo_access_for_stage(stage));
+
memcpy(&descriptors[i], view->bifrost_descriptor, sizeof(*view->bifrost_descriptor));
}
varyings[gl_FragCoord].elements = MALI_VARYING_FRAG_COORD;
struct panfrost_device *device = pan_device(ctx->base.screen);
- assert(!(device->quirks & IS_BIFROST) || !(reads_point_coord || fs->reads_face || fs->reads_frag_coord));
+ assert(!(device->quirks & IS_BIFROST) || !(reads_point_coord));
/* Let's go ahead and link varying meta to the buffer in question, now
* that that information is available. VARYING_SLOT_POS is mapped to
/* Set the type appropriately. TODO: Integer varyings XXX */
assert(o->stream == 0);
ovs[i].format = pan_xfb_format(o->num_components);
- ovs[i].swizzle = panfrost_get_default_swizzle(o->num_components);
+
+ if (device->quirks & HAS_SWIZZLES)
+ ovs[i].swizzle = panfrost_get_default_swizzle(o->num_components);
+ else
+ ovs[i].swizzle = panfrost_bifrost_swizzle(o->num_components);
/* Link to the fragment */
signed fs_idx = -1;