#include "pan_context.h"
#include "pan_job.h"
-/* TODO: Bifrost requires just a mali_shared_memory, without the rest of the
- * framebuffer */
+/* If a BO is accessed for a particular shader stage, will it be in the primary
+ * batch (vertex/tiler) or the secondary batch (fragment)? Anything but
+ * fragment will be primary, e.g. compute jobs will be considered
+ * "vertex/tiler" by analogy */
-void
+static inline uint32_t
+panfrost_bo_access_for_stage(enum pipe_shader_type stage)
+{
+ assert(stage == PIPE_SHADER_FRAGMENT ||
+ stage == PIPE_SHADER_VERTEX ||
+ stage == PIPE_SHADER_COMPUTE);
+
+ return stage == PIPE_SHADER_FRAGMENT ?
+ PAN_BO_ACCESS_FRAGMENT :
+ PAN_BO_ACCESS_VERTEX_TILER;
+}
+
+static void
+panfrost_vt_emit_shared_memory(struct panfrost_context *ctx,
+ struct mali_vertex_tiler_postfix *postfix)
+{
+ struct panfrost_device *dev = pan_device(ctx->base.screen);
+ struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
+
+ unsigned shift = panfrost_get_stack_shift(batch->stack_size);
+ struct mali_shared_memory shared = {
+ .stack_shift = shift,
+ .scratchpad = panfrost_batch_get_scratchpad(batch, shift, dev->thread_tls_alloc, dev->core_count)->gpu,
+ .shared_workgroup_count = ~0,
+ };
+ postfix->shared_memory = panfrost_upload_transient(batch, &shared, sizeof(shared));
+}
+
+static void
panfrost_vt_attach_framebuffer(struct panfrost_context *ctx,
- struct midgard_payload_vertex_tiler *vt)
+ struct mali_vertex_tiler_postfix *postfix)
{
- struct panfrost_screen *screen = pan_screen(ctx->base.screen);
+ struct panfrost_device *dev = pan_device(ctx->base.screen);
struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
/* If we haven't, reserve space for the framebuffer */
if (!batch->framebuffer.gpu) {
- unsigned size = (screen->quirks & MIDGARD_SFBD) ?
+ unsigned size = (dev->quirks & MIDGARD_SFBD) ?
sizeof(struct mali_single_framebuffer) :
sizeof(struct mali_framebuffer);
batch->framebuffer = panfrost_allocate_transient(batch, size);
/* Tag the pointer */
- if (!(screen->quirks & MIDGARD_SFBD))
+ if (!(dev->quirks & MIDGARD_SFBD))
batch->framebuffer.gpu |= MALI_MFBD;
}
- vt->postfix.shared_memory = batch->framebuffer.gpu;
+ postfix->shared_memory = batch->framebuffer.gpu;
}
-void
+static void
panfrost_vt_update_rasterizer(struct panfrost_context *ctx,
- struct midgard_payload_vertex_tiler *tp)
+ struct mali_vertex_tiler_prefix *prefix,
+ struct mali_vertex_tiler_postfix *postfix)
{
struct panfrost_rasterizer *rasterizer = ctx->rasterizer;
- tp->gl_enables |= 0x7;
- SET_BIT(tp->gl_enables, MALI_FRONT_CCW_TOP,
+ postfix->gl_enables |= 0x7;
+ SET_BIT(postfix->gl_enables, MALI_FRONT_CCW_TOP,
rasterizer && rasterizer->base.front_ccw);
- SET_BIT(tp->gl_enables, MALI_CULL_FACE_FRONT,
+ SET_BIT(postfix->gl_enables, MALI_CULL_FACE_FRONT,
rasterizer && (rasterizer->base.cull_face & PIPE_FACE_FRONT));
- SET_BIT(tp->gl_enables, MALI_CULL_FACE_BACK,
+ SET_BIT(postfix->gl_enables, MALI_CULL_FACE_BACK,
rasterizer && (rasterizer->base.cull_face & PIPE_FACE_BACK));
- SET_BIT(tp->prefix.unknown_draw, MALI_DRAW_FLATSHADE_FIRST,
+ SET_BIT(prefix->unknown_draw, MALI_DRAW_FLATSHADE_FIRST,
rasterizer && rasterizer->base.flatshade_first);
+}
+
+void
+panfrost_vt_update_primitive_size(struct panfrost_context *ctx,
+ struct mali_vertex_tiler_prefix *prefix,
+ union midgard_primitive_size *primitive_size)
+{
+ struct panfrost_rasterizer *rasterizer = ctx->rasterizer;
if (!panfrost_writes_point_size(ctx)) {
- bool points = tp->prefix.draw_mode == MALI_POINTS;
+ bool points = prefix->draw_mode == MALI_POINTS;
float val = 0.0f;
if (rasterizer)
rasterizer->base.point_size :
rasterizer->base.line_width;
- tp->primitive_size.constant = val;
+ primitive_size->constant = val;
}
}
-void
+static void
panfrost_vt_update_occlusion_query(struct panfrost_context *ctx,
- struct midgard_payload_vertex_tiler *tp)
+ struct mali_vertex_tiler_postfix *postfix)
{
- SET_BIT(tp->gl_enables, MALI_OCCLUSION_QUERY, ctx->occlusion_query);
+ SET_BIT(postfix->gl_enables, MALI_OCCLUSION_QUERY, ctx->occlusion_query);
if (ctx->occlusion_query)
- tp->postfix.occlusion_counter = ctx->occlusion_query->bo->gpu;
+ postfix->occlusion_counter = ctx->occlusion_query->bo->gpu;
else
- tp->postfix.occlusion_counter = 0;
+ postfix->occlusion_counter = 0;
}
void
panfrost_vt_init(struct panfrost_context *ctx,
enum pipe_shader_type stage,
- struct midgard_payload_vertex_tiler *vtp)
+ struct mali_vertex_tiler_prefix *prefix,
+ struct mali_vertex_tiler_postfix *postfix)
{
+ struct panfrost_device *device = pan_device(ctx->base.screen);
+
if (!ctx->shader[stage])
return;
- memset(vtp, 0, sizeof(*vtp));
- vtp->gl_enables = 0x6;
- panfrost_vt_attach_framebuffer(ctx, vtp);
+ memset(prefix, 0, sizeof(*prefix));
+ memset(postfix, 0, sizeof(*postfix));
+
+ if (device->quirks & IS_BIFROST) {
+ postfix->gl_enables = 0x2;
+ panfrost_vt_emit_shared_memory(ctx, postfix);
+ } else {
+ postfix->gl_enables = 0x6;
+ panfrost_vt_attach_framebuffer(ctx, postfix);
+ }
if (stage == PIPE_SHADER_FRAGMENT) {
- panfrost_vt_update_occlusion_query(ctx, vtp);
- panfrost_vt_update_rasterizer(ctx, vtp);
+ panfrost_vt_update_occlusion_query(ctx, postfix);
+ panfrost_vt_update_rasterizer(ctx, prefix, postfix);
}
}
-
static unsigned
panfrost_translate_index_size(unsigned size)
{
panfrost_vt_set_draw_info(struct panfrost_context *ctx,
const struct pipe_draw_info *info,
enum mali_draw_mode draw_mode,
- struct midgard_payload_vertex_tiler *vp,
- struct midgard_payload_vertex_tiler *tp,
+ struct mali_vertex_tiler_postfix *vertex_postfix,
+ struct mali_vertex_tiler_prefix *tiler_prefix,
+ struct mali_vertex_tiler_postfix *tiler_postfix,
unsigned *vertex_count,
unsigned *padded_count)
{
- tp->prefix.draw_mode = draw_mode;
+ tiler_prefix->draw_mode = draw_mode;
unsigned draw_flags = 0;
if (info->index_size) {
unsigned min_index = 0, max_index = 0;
- tp->prefix.indices = panfrost_get_index_buffer_bounded(ctx,
+ tiler_prefix->indices = panfrost_get_index_buffer_bounded(ctx,
info,
&min_index,
&max_index);
/* Use the corresponding values */
*vertex_count = max_index - min_index + 1;
- tp->offset_start = vp->offset_start = min_index + info->index_bias;
- tp->prefix.offset_bias_correction = -min_index;
- tp->prefix.index_count = MALI_POSITIVE(info->count);
+ tiler_postfix->offset_start = vertex_postfix->offset_start = min_index + info->index_bias;
+ tiler_prefix->offset_bias_correction = -min_index;
+ tiler_prefix->index_count = MALI_POSITIVE(info->count);
draw_flags |= panfrost_translate_index_size(info->index_size);
} else {
- tp->prefix.indices = 0;
+ tiler_prefix->indices = 0;
*vertex_count = ctx->vertex_count;
- tp->offset_start = vp->offset_start = info->start;
- tp->prefix.offset_bias_correction = 0;
- tp->prefix.index_count = MALI_POSITIVE(ctx->vertex_count);
+ tiler_postfix->offset_start = vertex_postfix->offset_start = info->start;
+ tiler_prefix->offset_bias_correction = 0;
+ tiler_prefix->index_count = MALI_POSITIVE(ctx->vertex_count);
}
- tp->prefix.unknown_draw = draw_flags;
+ tiler_prefix->unknown_draw = draw_flags;
/* Encode the padded vertex count */
unsigned shift = __builtin_ctz(ctx->padded_count);
unsigned k = ctx->padded_count >> (shift + 1);
- tp->instance_shift = vp->instance_shift = shift;
- tp->instance_odd = vp->instance_odd = k;
+ tiler_postfix->instance_shift = vertex_postfix->instance_shift = shift;
+ tiler_postfix->instance_odd = vertex_postfix->instance_odd = k;
} else {
*padded_count = *vertex_count;
/* Reset instancing state */
- tp->instance_shift = vp->instance_shift = 0;
- tp->instance_odd = vp->instance_odd = 0;
+ tiler_postfix->instance_shift = vertex_postfix->instance_shift = 0;
+ tiler_postfix->instance_odd = vertex_postfix->instance_odd = 0;
}
}
enum pipe_shader_type st,
struct mali_shader_meta *meta)
{
+ const struct panfrost_device *dev = pan_device(ctx->base.screen);
struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st);
memset(meta, 0, sizeof(*meta));
meta->shader = (ss->bo ? ss->bo->gpu : 0) | ss->first_tag;
- meta->midgard1.uniform_count = MIN2(ss->uniform_count,
- ss->uniform_cutoff);
- meta->midgard1.work_count = ss->work_reg_count;
meta->attribute_count = ss->attribute_count;
meta->varying_count = ss->varying_count;
- meta->midgard1.flags_hi = 0x8; /* XXX */
- meta->midgard1.flags_lo = 0x220;
meta->texture_count = ctx->sampler_view_count[st];
meta->sampler_count = ctx->sampler_count[st];
- meta->midgard1.uniform_buffer_count = panfrost_ubo_count(ctx, st);
+
+ if (dev->quirks & IS_BIFROST) {
+ meta->bifrost1.unk1 = 0x800200;
+ meta->bifrost1.uniform_buffer_count = panfrost_ubo_count(ctx, st);
+ meta->bifrost2.preload_regs = 0xC0;
+ meta->bifrost2.uniform_count = MIN2(ss->uniform_count,
+ ss->uniform_cutoff);
+ } else {
+ meta->midgard1.uniform_count = MIN2(ss->uniform_count,
+ ss->uniform_cutoff);
+ meta->midgard1.work_count = ss->work_reg_count;
+ meta->midgard1.flags_hi = 0x8; /* XXX */
+ meta->midgard1.flags_lo = 0x220;
+ meta->midgard1.uniform_buffer_count = panfrost_ubo_count(ctx, st);
+ }
+
}
static unsigned
struct mali_shader_meta *fragmeta,
struct midgard_blend_rt *rts)
{
- const struct panfrost_screen *screen = pan_screen(ctx->base.screen);
+ const struct panfrost_device *dev = pan_device(ctx->base.screen);
SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER,
- (screen->quirks & MIDGARD_SFBD) && ctx->blend &&
+ (dev->quirks & MIDGARD_SFBD) && ctx->blend &&
!ctx->blend->base.dither);
/* Get blending setup */
break;
}
- if (screen->quirks & MIDGARD_SFBD) {
+ if (dev->quirks & MIDGARD_SFBD) {
/* When only a single render target platform is used, the blend
* information is inside the shader meta itself. We additionally
* need to signal CAN_DISCARD for nontrivial blend modes (so
struct mali_shader_meta *fragmeta,
struct midgard_blend_rt *rts)
{
- const struct panfrost_screen *screen = pan_screen(ctx->base.screen);
+ const struct panfrost_device *dev = pan_device(ctx->base.screen);
struct panfrost_shader_state *fs;
fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
* these earlier chips (perhaps this is a chicken bit of some kind).
* More investigation is needed. */
- SET_BIT(fragmeta->unknown2_4, 0x10, screen->quirks & MIDGARD_SFBD);
+ SET_BIT(fragmeta->unknown2_4, 0x10, dev->quirks & MIDGARD_SFBD);
/* Depending on whether it's legal to in the given shader, we try to
* enable early-z testing (or forward-pixel kill?) */
void
panfrost_emit_shader_meta(struct panfrost_batch *batch,
enum pipe_shader_type st,
- struct midgard_payload_vertex_tiler *vtp)
+ struct mali_vertex_tiler_postfix *postfix)
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st);
if (!ss) {
- vtp->postfix.shader = 0;
+ postfix->shader = 0;
return;
}
mali_ptr shader_ptr;
if (st == PIPE_SHADER_FRAGMENT) {
- struct panfrost_screen *screen = pan_screen(ctx->base.screen);
+ struct panfrost_device *dev = pan_device(ctx->base.screen);
unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1);
size_t desc_size = sizeof(meta);
struct midgard_blend_rt rts[4];
panfrost_frag_shader_meta_init(ctx, &meta, rts);
- if (!(screen->quirks & MIDGARD_SFBD))
+ if (!(dev->quirks & MIDGARD_SFBD))
desc_size += sizeof(*rts) * rt_count;
xfer = panfrost_allocate_transient(batch, desc_size);
sizeof(meta));
}
- vtp->postfix.shader = shader_ptr;
+ postfix->shader = shader_ptr;
}
static void
void
panfrost_emit_viewport(struct panfrost_batch *batch,
- struct midgard_payload_vertex_tiler *tp)
+ struct mali_vertex_tiler_postfix *tiler_postfix)
{
struct panfrost_context *ctx = batch->ctx;
struct mali_viewport mvp;
mvp.viewport1[0] + 1,
mvp.viewport1[1] + 1);
- tp->postfix.viewport = panfrost_upload_transient(batch, &mvp,
- sizeof(mvp));
+ tiler_postfix->viewport = panfrost_upload_transient(batch, &mvp,
+ sizeof(mvp));
}
static mali_ptr
void
panfrost_emit_const_buf(struct panfrost_batch *batch,
enum pipe_shader_type stage,
- struct midgard_payload_vertex_tiler *vtp)
+ struct mali_vertex_tiler_postfix *postfix)
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_shader_variants *all = ctx->shader[stage];
memcpy(transfer.cpu + sys_size, cpu, uniform_size);
}
- struct mali_vertex_tiler_postfix *postfix = &vtp->postfix;
-
/* Next up, attach UBOs. UBO #0 is the uniforms we just
* uploaded */
void
panfrost_emit_texture_descriptors(struct panfrost_batch *batch,
enum pipe_shader_type stage,
- struct midgard_payload_vertex_tiler *vtp)
+ struct mali_vertex_tiler_postfix *postfix)
{
struct panfrost_context *ctx = batch->ctx;
trampolines[i] = panfrost_get_tex_desc(batch, stage,
ctx->sampler_views[stage][i]);
- vtp->postfix.texture_trampoline = panfrost_upload_transient(batch,
- trampolines,
- sizeof(uint64_t) *
- ctx->sampler_view_count[stage]);
+ postfix->texture_trampoline = panfrost_upload_transient(batch,
+ trampolines,
+ sizeof(uint64_t) *
+ ctx->sampler_view_count[stage]);
}
void
panfrost_emit_sampler_descriptors(struct panfrost_batch *batch,
enum pipe_shader_type stage,
- struct midgard_payload_vertex_tiler *vtp)
+ struct mali_vertex_tiler_postfix *postfix)
{
struct panfrost_context *ctx = batch->ctx;
for (int i = 0; i < ctx->sampler_count[stage]; ++i)
desc[i] = ctx->samplers[stage][i]->hw;
- vtp->postfix.sampler_descriptor = transfer.gpu;
+ postfix->sampler_descriptor = transfer.gpu;
}
void
panfrost_emit_vertex_attr_meta(struct panfrost_batch *batch,
- struct midgard_payload_vertex_tiler *vp)
+ struct mali_vertex_tiler_postfix *vertex_postfix)
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_vertex_state *so = ctx->vertex;
- panfrost_vertex_state_upd_attr_offs(ctx, vp);
- vp->postfix.attribute_meta = panfrost_upload_transient(batch, so->hw,
+ panfrost_vertex_state_upd_attr_offs(ctx, vertex_postfix);
+ vertex_postfix->attribute_meta = panfrost_upload_transient(batch, so->hw,
sizeof(*so->hw) *
PAN_MAX_ATTRIBUTE);
}
void
panfrost_emit_vertex_data(struct panfrost_batch *batch,
- struct midgard_payload_vertex_tiler *vp)
+ struct mali_vertex_tiler_postfix *vertex_postfix)
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_vertex_state *so = ctx->vertex;
/* Normal, non-instanced attributes */
attrs[k++].elements |= MALI_ATTR_LINEAR;
} else {
- unsigned instance_shift = vp->instance_shift;
- unsigned instance_odd = vp->instance_odd;
+ unsigned instance_shift = vertex_postfix->instance_shift;
+ unsigned instance_odd = vertex_postfix->instance_odd;
k += panfrost_vertex_instanced(ctx->padded_count,
instance_shift,
/* Upload whatever we emitted and go */
- vp->postfix.attributes = panfrost_upload_transient(batch, attrs,
+ vertex_postfix->attributes = panfrost_upload_transient(batch, attrs,
k * sizeof(*attrs));
}
void
panfrost_emit_varying_descriptor(struct panfrost_batch *batch,
unsigned vertex_count,
- struct midgard_payload_vertex_tiler *vp,
- struct midgard_payload_vertex_tiler *tp)
+ struct mali_vertex_tiler_postfix *vertex_postfix,
+ struct mali_vertex_tiler_postfix *tiler_postfix,
+ union midgard_primitive_size *primitive_size)
{
/* Load the shaders */
struct panfrost_context *ctx = batch->ctx;
/* fp32 vec4 gl_Position */
varyings_p = panfrost_emit_varyings(batch, &varyings[gl_Position],
sizeof(float) * 4, vertex_count);
- tp->postfix.position_varying = varyings_p;
+ tiler_postfix->position_varying = varyings_p;
if (panfrost_writes_point_size(ctx)) {
varyings_p = panfrost_emit_varyings(batch,
&varyings[gl_PointSize],
2, vertex_count);
- tp->primitive_size.pointer = varyings_p;
+ primitive_size->pointer = varyings_p;
}
if (reads_point_coord)
varyings_p = panfrost_upload_transient(batch, varyings,
idx * sizeof(*varyings));
- vp->postfix.varyings = varyings_p;
- tp->postfix.varyings = varyings_p;
+ vertex_postfix->varyings = varyings_p;
+ tiler_postfix->varyings = varyings_p;
- vp->postfix.varying_meta = trans.gpu;
- tp->postfix.varying_meta = trans.gpu + vs_size;
+ vertex_postfix->varying_meta = trans.gpu;
+ tiler_postfix->varying_meta = trans.gpu + vs_size;
}
void
panfrost_emit_vertex_tiler_jobs(struct panfrost_batch *batch,
- struct midgard_payload_vertex_tiler *vp,
- struct midgard_payload_vertex_tiler *tp)
+ struct mali_vertex_tiler_prefix *vertex_prefix,
+ struct mali_vertex_tiler_postfix *vertex_postfix,
+ struct mali_vertex_tiler_prefix *tiler_prefix,
+ struct mali_vertex_tiler_postfix *tiler_postfix,
+ union midgard_primitive_size *primitive_size)
{
struct panfrost_context *ctx = batch->ctx;
+ struct panfrost_device *device = pan_device(ctx->base.screen);
bool wallpapering = ctx->wallpaper_batch && batch->tiler_dep;
+ struct bifrost_payload_vertex bifrost_vertex = {0,};
+ struct bifrost_payload_tiler bifrost_tiler = {0,};
+ struct midgard_payload_vertex_tiler midgard_vertex = {0,};
+ struct midgard_payload_vertex_tiler midgard_tiler = {0,};
+ void *vp, *tp;
+ size_t vp_size, tp_size;
+
+ if (device->quirks & IS_BIFROST) {
+ bifrost_vertex.prefix = *vertex_prefix;
+ bifrost_vertex.postfix = *vertex_postfix;
+ vp = &bifrost_vertex;
+ vp_size = sizeof(bifrost_vertex);
+
+ bifrost_tiler.prefix = *tiler_prefix;
+ bifrost_tiler.tiler.primitive_size = *primitive_size;
+ //bifrost_tiler.tiler.tiler_meta;
+ bifrost_tiler.postfix = *tiler_postfix;
+ tp = &bifrost_tiler;
+ tp_size = sizeof(bifrost_tiler);
+ } else {
+ midgard_vertex.prefix = *vertex_prefix;
+ midgard_vertex.postfix = *vertex_postfix;
+ vp = &midgard_vertex;
+ vp_size = sizeof(midgard_vertex);
+
+ midgard_tiler.prefix = *tiler_prefix;
+ midgard_tiler.postfix = *tiler_postfix;
+ midgard_tiler.primitive_size = *primitive_size;
+ tp = &midgard_tiler;
+ tp_size = sizeof(midgard_tiler);
+ }
if (wallpapering) {
/* Inject in reverse order, with "predicted" job indices.
* THIS IS A HACK XXX */
panfrost_new_job(batch, JOB_TYPE_TILER, false,
- batch->job_index + 2, tp, sizeof(*tp), true);
+ batch->job_index + 2, tp, tp_size, true);
panfrost_new_job(batch, JOB_TYPE_VERTEX, false, 0,
- vp, sizeof(*vp), true);
+ vp, vp_size, true);
return;
}
ctx->rasterizer->base.rasterizer_discard;
unsigned vertex = panfrost_new_job(batch, JOB_TYPE_VERTEX, false, 0,
- vp, sizeof(*vp), false);
+ vp, vp_size, false);
if (rasterizer_discard)
return;
- panfrost_new_job(batch, JOB_TYPE_TILER, false, vertex, tp, sizeof(*tp),
+ panfrost_new_job(batch, JOB_TYPE_TILER, false, vertex, tp, tp_size,
false);
}
projects / mesa.git / blobdiff