#include "util/half_float.h"
#include "util/u_helpers.h"
#include "util/u_format.h"
+#include "util/u_prim_restart.h"
#include "indices/u_primconvert.h"
#include "tgsi/tgsi_parse.h"
#include "util/u_math.h"
}
}
-static void
-panfrost_enable_checksum(struct panfrost_context *ctx, struct panfrost_resource *rsrc)
-{
- struct pipe_context *gallium = (struct pipe_context *) ctx;
- struct panfrost_screen *screen = pan_screen(gallium->screen);
- int tile_w = (rsrc->base.width0 + (MALI_TILE_LENGTH - 1)) >> MALI_TILE_SHIFT;
- int tile_h = (rsrc->base.height0 + (MALI_TILE_LENGTH - 1)) >> MALI_TILE_SHIFT;
-
- /* 8 byte checksum per tile */
- rsrc->bo->checksum_stride = tile_w * 8;
- int pages = (((rsrc->bo->checksum_stride * tile_h) + 4095) / 4096);
- panfrost_drm_allocate_slab(screen, &rsrc->bo->checksum_slab, pages, false, 0, 0, 0);
-
- rsrc->bo->has_checksum = true;
-}
-
/* Framebuffer descriptor */
static void
.unknown2 = 0x1f,
.format = 0x30000000,
.clear_flags = 0x1000,
- .unknown_address_0 = ctx->scratchpad.gpu,
- .tiler_polygon_list = ctx->tiler_polygon_list.gpu,
- .tiler_polygon_list_body = ctx->tiler_polygon_list.gpu + 40960,
+ .unknown_address_0 = ctx->scratchpad.bo->gpu,
+ .tiler_polygon_list = ctx->tiler_polygon_list.bo->gpu,
+ .tiler_polygon_list_body = ctx->tiler_polygon_list.bo->gpu + 40960,
.tiler_hierarchy_mask = 0xF0,
.tiler_flags = 0x0,
- .tiler_heap_free = ctx->tiler_heap.gpu,
- .tiler_heap_end = ctx->tiler_heap.gpu + ctx->tiler_heap.size,
+ .tiler_heap_free = ctx->tiler_heap.bo->gpu,
+ .tiler_heap_end = ctx->tiler_heap.bo->gpu + ctx->tiler_heap.bo->size,
};
panfrost_set_framebuffer_resolution(&framebuffer, ctx->pipe_framebuffer.width, ctx->pipe_framebuffer.height);
.unknown2 = 0x1f,
- .scratchpad = ctx->scratchpad.gpu,
+ .scratchpad = ctx->scratchpad.bo->gpu,
};
framebuffer.tiler_hierarchy_mask =
unsigned total_size = header_size + body_size;
if (framebuffer.tiler_hierarchy_mask) {
- assert(ctx->tiler_polygon_list.size >= total_size);
+ assert(ctx->tiler_polygon_list.bo->size >= total_size);
/* Specify allocated tiler structures */
- framebuffer.tiler_polygon_list = ctx->tiler_polygon_list.gpu;
+ framebuffer.tiler_polygon_list = ctx->tiler_polygon_list.bo->gpu;
/* Allow the entire tiler heap */
- framebuffer.tiler_heap_start = ctx->tiler_heap.gpu;
+ framebuffer.tiler_heap_start = ctx->tiler_heap.bo->gpu;
framebuffer.tiler_heap_end =
- ctx->tiler_heap.gpu + ctx->tiler_heap.size;
+ ctx->tiler_heap.bo->gpu + ctx->tiler_heap.bo->size;
} else {
/* The tiler is disabled, so don't allow the tiler heap */
- framebuffer.tiler_heap_start = ctx->tiler_heap.gpu;
+ framebuffer.tiler_heap_start = ctx->tiler_heap.bo->gpu;
framebuffer.tiler_heap_end = framebuffer.tiler_heap_start;
/* Use a dummy polygon list */
- framebuffer.tiler_polygon_list = ctx->tiler_dummy.gpu;
+ framebuffer.tiler_polygon_list = ctx->tiler_dummy.bo->gpu;
/* Also, set a "tiler disabled?" flag? */
framebuffer.tiler_hierarchy_mask |= 0x1000;
panfrost_emit_vertex_payload(struct panfrost_context *ctx)
{
struct midgard_payload_vertex_tiler payload = {
- .prefix = {
- .workgroups_z_shift = 32,
- .workgroups_x_shift_2 = 0x2,
- .workgroups_x_shift_3 = 0x5,
- },
.gl_enables = 0x4 | (ctx->is_t6xx ? 0 : 0x2),
};
{
struct midgard_payload_vertex_tiler payload = {
.prefix = {
- .workgroups_z_shift = 32,
- .workgroups_x_shift_2 = 0x2,
- .workgroups_x_shift_3 = 0x6,
-
.zero1 = 0xffff, /* Why is this only seen on test-quad-textured? */
},
};
unsigned stride,
unsigned count)
{
- mali_ptr varying_address = ctx->varying_mem.gpu + ctx->varying_height;
+ mali_ptr varying_address = ctx->varying_mem.bo->gpu + ctx->varying_height;
/* Fill out the descriptor */
slot->elements = varying_address | MALI_ATTR_LINEAR;
slot->stride = stride;
slot->size = stride * count;
- ctx->varying_height += ALIGN(slot->size, 64);
- assert(ctx->varying_height < ctx->varying_mem.size);
+ ctx->varying_height += ALIGN_POT(slot->size, 64);
+ assert(ctx->varying_height < ctx->varying_mem.bo->size);
return varying_address;
}
static void
panfrost_emit_varying_descriptor(
struct panfrost_context *ctx,
- unsigned invocation_count)
+ unsigned vertex_count)
{
/* Load the shaders */
for (unsigned i = 0; i < fs->tripipe->varying_count; i++) {
unsigned j;
+ /* If we have a point sprite replacement, handle that here. We
+ * have to translate location first. TODO: Flip y in shader.
+ * We're already keying ... just time crunch .. */
+
+ unsigned loc = fs->varyings_loc[i];
+ unsigned pnt_loc =
+ (loc >= VARYING_SLOT_VAR0) ? (loc - VARYING_SLOT_VAR0) :
+ (loc == VARYING_SLOT_PNTC) ? 8 :
+ ~0;
+
+ if (~pnt_loc && fs->point_sprite_mask & (1 << pnt_loc)) {
+ /* gl_PointCoord index by convention */
+ fs->varyings[i].index = 3;
+ fs->reads_point_coord = true;
+
+ /* Swizzle out the z/w to 0/1 */
+ fs->varyings[i].format = MALI_RG16F;
+ fs->varyings[i].swizzle =
+ panfrost_get_default_swizzle(2);
+
+ continue;
+ }
+
if (fs->varyings[i].index)
continue;
unsigned idx = 0;
panfrost_emit_varyings(ctx, &varyings[idx++], num_gen_varyings * 16,
- invocation_count);
+ vertex_count);
/* fp32 vec4 gl_Position */
ctx->payload_tiler.postfix.position_varying =
panfrost_emit_varyings(ctx, &varyings[idx++],
- sizeof(float) * 4, invocation_count);
+ sizeof(float) * 4, vertex_count);
if (vs->writes_point_size || fs->reads_point_coord) {
/* fp16 vec1 gl_PointSize */
ctx->payload_tiler.primitive_size.pointer =
panfrost_emit_varyings(ctx, &varyings[idx++],
- 2, invocation_count);
+ 2, vertex_count);
}
if (fs->reads_point_coord) {
ctx->payload_tiler.postfix.varyings = varyings_p;
}
-static mali_ptr
+mali_ptr
panfrost_vertex_buffer_address(struct panfrost_context *ctx, unsigned i)
{
struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[i];
return rsrc->bo->gpu + buf->buffer_offset;
}
-/* Emits attributes and varying descriptors, which should be called every draw,
- * excepting some obscure circumstances */
-
-static void
-panfrost_emit_vertex_data(struct panfrost_context *ctx, struct panfrost_job *job)
-{
- /* Staged mali_attr, and index into them. i =/= k, depending on the
- * vertex buffer mask */
- union mali_attr attrs[PIPE_MAX_ATTRIBS];
- unsigned k = 0;
-
- unsigned invocation_count = MALI_NEGATIVE(ctx->payload_tiler.prefix.invocation_count);
-
- for (int i = 0; i < ARRAY_SIZE(ctx->vertex_buffers); ++i) {
- if (!(ctx->vb_mask & (1 << i))) continue;
-
- struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[i];
- struct panfrost_resource *rsrc = (struct panfrost_resource *) (buf->buffer.resource);
-
- if (!rsrc) continue;
-
- /* Align to 64 bytes by masking off the lower bits. This
- * will be adjusted back when we fixup the src_offset in
- * mali_attr_meta */
-
- mali_ptr addr = panfrost_vertex_buffer_address(ctx, i) & ~63;
-
- /* Offset vertex count by draw_start to make sure we upload enough */
- attrs[k].stride = buf->stride;
- attrs[k].size = rsrc->base.width0;
-
- panfrost_job_add_bo(job, rsrc->bo);
- attrs[k].elements = addr | MALI_ATTR_LINEAR;
-
- ++k;
- }
-
- ctx->payload_vertex.postfix.attributes = panfrost_upload_transient(ctx, attrs, k * sizeof(union mali_attr));
-
- panfrost_emit_varying_descriptor(ctx, invocation_count);
-}
-
static bool
panfrost_writes_point_size(struct panfrost_context *ctx)
{
* QED.
*/
+ unsigned start = ctx->payload_vertex.draw_start;
+
for (unsigned i = 0; i < so->num_elements; ++i) {
unsigned vbi = so->pipe[i].vertex_buffer_index;
+ struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi];
mali_ptr addr = panfrost_vertex_buffer_address(ctx, vbi);
/* Adjust by the masked off bits of the offset */
target[i].src_offset += (addr & 63);
+
+ /* Also, somewhat obscurely per-instance data needs to be
+ * offset in response to a delayed start in an indexed draw */
+
+ if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start) {
+ target[i].src_offset -= buf->stride * start;
+ }
+
+
}
ctx->payload_vertex.postfix.attribute_meta = transfer.gpu;
}
}
-/* Computes the address to a texture at a particular slice */
-
-static mali_ptr
-panfrost_get_texture_address(
- struct panfrost_resource *rsrc,
- unsigned level, unsigned face)
-{
- unsigned level_offset = rsrc->bo->slices[level].offset;
- unsigned face_offset = face * rsrc->bo->cubemap_stride;
-
- return rsrc->bo->gpu + level_offset + face_offset;
-
-}
-
static mali_ptr
panfrost_upload_tex(
struct panfrost_context *ctx,
assert(pview->target != PIPE_BUFFER);
unsigned first_level = pview->u.tex.first_level;
unsigned last_level = pview->u.tex.last_level;
+ unsigned first_layer = pview->u.tex.first_layer;
+ unsigned last_layer = pview->u.tex.last_layer;
+
+ /* Lower-bit is set when sampling from colour AFBC */
+ bool is_afbc = rsrc->layout == PAN_AFBC;
+ bool is_zs = rsrc->base.bind & PIPE_BIND_DEPTH_STENCIL;
+ unsigned afbc_bit = (is_afbc && !is_zs) ? 1 : 0;
+
+ /* Add the BO to the job so it's retained until the job is done. */
+ struct panfrost_job *job = panfrost_get_job_for_fbo(ctx);
+ panfrost_job_add_bo(job, rsrc->bo);
/* Inject the addresses in, interleaving mip levels, cube faces, and
* strides in that order */
unsigned idx = 0;
for (unsigned l = first_level; l <= last_level; ++l) {
- for (unsigned f = 0; f < pview->texture->array_size; ++f) {
+ for (unsigned f = first_layer; f <= last_layer; ++f) {
+
view->hw.payload[idx++] =
- panfrost_get_texture_address(rsrc, l, f);
+ panfrost_get_texture_address(rsrc, l, f) + afbc_bit;
if (has_manual_stride) {
view->hw.payload[idx++] =
- rsrc->bo->slices[l].stride;
+ rsrc->slices[l].stride;
}
}
}
}
}
+static const void *
+panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer *buf, unsigned index)
+{
+ struct pipe_constant_buffer *cb = &buf->cb[index];
+ struct panfrost_resource *rsrc = pan_resource(cb->buffer);
+
+ if (rsrc)
+ return rsrc->bo->cpu;
+ else if (cb->user_buffer)
+ return cb->user_buffer;
+ else
+ unreachable("No constant buffer");
+}
+
+static mali_ptr
+panfrost_map_constant_buffer_gpu(
+ struct panfrost_context *ctx,
+ struct panfrost_constant_buffer *buf,
+ unsigned index)
+{
+ struct pipe_constant_buffer *cb = &buf->cb[index];
+ struct panfrost_resource *rsrc = pan_resource(cb->buffer);
+
+ if (rsrc)
+ return rsrc->bo->gpu;
+ else if (cb->user_buffer)
+ return panfrost_upload_transient(ctx, cb->user_buffer, cb->buffer_size);
+ else
+ unreachable("No constant buffer");
+}
+
+/* Compute number of UBOs active (more specifically, compute the highest UBO
+ * number addressable -- if there are gaps, include them in the count anyway).
+ * We always include UBO #0 in the count, since we *need* uniforms enabled for
+ * sysvals. */
+
+static unsigned
+panfrost_ubo_count(struct panfrost_context *ctx, enum pipe_shader_type stage)
+{
+ unsigned mask = ctx->constant_buffer[stage].enabled_mask | 1;
+ return 32 - __builtin_clz(mask);
+}
+
+/* Fixes up a shader state with current state, returning a GPU address to the
+ * patched shader */
+
+static mali_ptr
+panfrost_patch_shader_state(
+ struct panfrost_context *ctx,
+ struct panfrost_shader_state *ss,
+ enum pipe_shader_type stage)
+{
+ ss->tripipe->texture_count = ctx->sampler_view_count[stage];
+ ss->tripipe->sampler_count = ctx->sampler_count[stage];
+
+ ss->tripipe->midgard1.flags = 0x220;
+
+ unsigned ubo_count = panfrost_ubo_count(ctx, stage);
+ ss->tripipe->midgard1.uniform_buffer_count = ubo_count;
+
+ return ss->tripipe_gpu;
+}
+
/* Go through dirty flags and actualise them in the cmdstream. */
void
struct panfrost_job *job = panfrost_get_job_for_fbo(ctx);
if (with_vertex_data) {
- panfrost_emit_vertex_data(ctx, job);
+ panfrost_emit_vertex_data(job);
+
+ /* Varyings emitted for -all- geometry */
+ unsigned total_count = ctx->padded_count * ctx->instance_count;
+ panfrost_emit_varying_descriptor(ctx, total_count);
}
bool msaa = ctx->rasterizer->base.multisample;
struct panfrost_shader_state *vs = &ctx->vs->variants[ctx->vs->active_variant];
- /* Late shader descriptor assignments */
-
- vs->tripipe->texture_count = ctx->sampler_view_count[PIPE_SHADER_VERTEX];
- vs->tripipe->sampler_count = ctx->sampler_count[PIPE_SHADER_VERTEX];
-
- /* Who knows */
- vs->tripipe->midgard1.unknown1 = 0x2201;
-
- ctx->payload_vertex.postfix._shader_upper = vs->tripipe_gpu >> 4;
+ ctx->payload_vertex.postfix._shader_upper =
+ panfrost_patch_shader_state(ctx, vs, PIPE_SHADER_VERTEX) >> 4;
}
if (ctx->dirty & (PAN_DIRTY_RASTERIZER | PAN_DIRTY_VS)) {
assert(ctx->fs);
struct panfrost_shader_state *variant = &ctx->fs->variants[ctx->fs->active_variant];
+ panfrost_patch_shader_state(ctx, variant, PIPE_SHADER_FRAGMENT);
+
#define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
COPY(shader);
COPY(attribute_count);
COPY(varying_count);
+ COPY(texture_count);
+ COPY(sampler_count);
+ COPY(sampler_count);
COPY(midgard1.uniform_count);
+ COPY(midgard1.uniform_buffer_count);
COPY(midgard1.work_count);
+ COPY(midgard1.flags);
COPY(midgard1.unknown2);
#undef COPY
ctx->fragment_shader_core.midgard1.work_count = /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
/* Set late due to depending on render state */
- /* The one at the end seems to mean "1 UBO" */
- unsigned flags = MALI_EARLY_Z | 0x200 | 0x2000 | 0x1;
+ unsigned flags = ctx->fragment_shader_core.midgard1.flags;
+
+ /* Depending on whether it's legal to in the given shader, we
+ * try to enable early-z testing (or forward-pixel kill?) */
+
+ if (!variant->can_discard)
+ flags |= MALI_EARLY_Z;
/* Any time texturing is used, derivatives are implicitly
* calculated, so we need to enable helper invocations */
if (ctx->sampler_view_count[PIPE_SHADER_FRAGMENT])
flags |= MALI_HELPER_INVOCATIONS;
- ctx->fragment_shader_core.midgard1.unknown1 = flags;
-
- /* Assign texture/sample count right before upload */
- ctx->fragment_shader_core.texture_count = ctx->sampler_view_count[PIPE_SHADER_FRAGMENT];
- ctx->fragment_shader_core.sampler_count = ctx->sampler_count[PIPE_SHADER_FRAGMENT];
+ ctx->fragment_shader_core.midgard1.flags = flags;
/* Assign the stencil refs late */
ctx->fragment_shader_core.stencil_front.ref = ctx->stencil_ref.ref_value[0];
if (variant->can_discard) {
ctx->fragment_shader_core.unknown2_3 |= MALI_CAN_DISCARD;
- ctx->fragment_shader_core.midgard1.unknown1 &= ~MALI_EARLY_Z;
- ctx->fragment_shader_core.midgard1.unknown1 |= 0x4000;
- ctx->fragment_shader_core.midgard1.unknown1 = 0x4200;
+ ctx->fragment_shader_core.midgard1.flags |= 0x400;
}
/* Check if we're using the default blend descriptor (fast path) */
struct panfrost_shader_state *fs = &ctx->fs->variants[ctx->fs->active_variant];
struct panfrost_shader_state *ss = (i == PIPE_SHADER_FRAGMENT) ? fs : vs;
+ /* Uniforms are implicitly UBO #0 */
+ bool has_uniforms = buf->enabled_mask & (1 << 0);
+
/* Allocate room for the sysval and the uniforms */
size_t sys_size = sizeof(float) * 4 * ss->sysval_count;
- size_t size = sys_size + buf->size;
+ size_t uniform_size = has_uniforms ? (buf->cb[0].buffer_size) : 0;
+ size_t size = sys_size + uniform_size;
struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, size);
/* Upload sysvals requested by the shader */
panfrost_upload_sysvals(ctx, transfer.cpu, ss, i);
/* Upload uniforms */
- memcpy(transfer.cpu + sys_size, buf->buffer, buf->size);
+ if (has_uniforms) {
+ const void *cpu = panfrost_map_constant_buffer_cpu(buf, 0);
+ memcpy(transfer.cpu + sys_size, cpu, uniform_size);
+ }
int uniform_count = 0;
unreachable("Invalid shader stage\n");
}
- /* Also attach the same buffer as a UBO for extended access */
+ /* Next up, attach UBOs. UBO #0 is the uniforms we just
+ * uploaded */
+
+ unsigned ubo_count = panfrost_ubo_count(ctx, i);
+ assert(ubo_count >= 1);
+
+ size_t sz = sizeof(struct mali_uniform_buffer_meta) * ubo_count;
+ struct mali_uniform_buffer_meta *ubos = calloc(sz, 1);
+
+ /* Upload uniforms as a UBO */
+ ubos[0].size = MALI_POSITIVE((2 + uniform_count));
+ ubos[0].ptr = transfer.gpu >> 2;
+
+ /* The rest are honest-to-goodness UBOs */
+
+ for (unsigned ubo = 1; ubo < ubo_count; ++ubo) {
+ size_t sz = buf->cb[ubo].buffer_size;
- struct mali_uniform_buffer_meta uniform_buffers[] = {
- {
- .size = MALI_POSITIVE((2 + uniform_count)),
- .ptr = transfer.gpu >> 2,
- },
- };
+ bool enabled = buf->enabled_mask & (1 << ubo);
+ bool empty = sz == 0;
- mali_ptr ubufs = panfrost_upload_transient(ctx, uniform_buffers, sizeof(uniform_buffers));
+ if (!enabled || empty) {
+ /* Stub out disabled UBOs to catch accesses */
+
+ ubos[ubo].size = 0;
+ ubos[ubo].ptr = 0xDEAD0000;
+ continue;
+ }
+
+ mali_ptr gpu = panfrost_map_constant_buffer_gpu(ctx, buf, ubo);
+
+ unsigned bytes_per_field = 16;
+ unsigned aligned = ALIGN_POT(sz, bytes_per_field);
+ unsigned fields = aligned / bytes_per_field;
+
+ ubos[ubo].size = MALI_POSITIVE(fields);
+ ubos[ubo].ptr = gpu >> 2;
+ }
+
+ mali_ptr ubufs = panfrost_upload_transient(ctx, ubos, sz);
postfix->uniforms = transfer.gpu;
postfix->uniform_buffers = ubufs;
- buf->dirty = 0;
+ buf->dirty_mask = 0;
}
/* TODO: Upload the viewport somewhere more appropriate */
* should work, but in practice causes issues when we're not
* explicitly trying to scissor */
- .clip_minx = -inff,
- .clip_miny = -inff,
- .clip_maxx = inff,
- .clip_maxy = inff,
+ .clip_minx = -INFINITY,
+ .clip_miny = -INFINITY,
+ .clip_maxx = INFINITY,
+ .clip_maxy = INFINITY,
.clip_minz = 0.0,
.clip_maxz = 1.0,
struct panfrost_resource *rsrc = pan_resource(surf->texture);
unsigned level = surf->u.tex.level;
- if (!rsrc->bo->slices[level].initialized)
+ if (!rsrc->slices[level].initialized)
return;
/* Save the batch */
struct panfrost_resource *rsrc = (struct panfrost_resource *) (info->index.resource);
off_t offset = info->start * info->index_size;
+ struct panfrost_job *batch = panfrost_get_job_for_fbo(ctx);
if (!info->has_user_indices) {
/* Only resources can be directly mapped */
+ panfrost_job_add_bo(batch, rsrc->bo);
return rsrc->bo->gpu + offset;
} else {
/* Otherwise, we need to upload to transient memory */
/* Check if we're scissoring at all */
- if (!(ss && ctx->rasterizer && ctx->rasterizer->base.scissor))
+ if (!(ctx->rasterizer && ctx->rasterizer->base.scissor))
return false;
- return (ss->minx == ss->maxx) && (ss->miny == ss->maxy);
+ return (ss->minx == ss->maxx) || (ss->miny == ss->maxy);
}
static void
int mode = info->mode;
+ /* Fallback unsupported restart index */
+ unsigned primitive_index = (1 << (info->index_size * 8)) - 1;
+
+ if (info->primitive_restart && info->index_size
+ && info->restart_index != primitive_index) {
+ util_draw_vbo_without_prim_restart(pipe, info);
+ return;
+ }
+
/* Fallback for unsupported modes */
if (!(ctx->draw_modes & (1 << mode))) {
ctx->payload_tiler.prefix.draw_mode = g2m_draw_mode(mode);
ctx->vertex_count = info->count;
+ ctx->instance_count = info->instance_count;
/* For non-indexed draws, they're the same */
- unsigned invocation_count = ctx->vertex_count;
+ unsigned vertex_count = ctx->vertex_count;
unsigned draw_flags = 0;
if (panfrost_writes_point_size(ctx))
draw_flags |= MALI_DRAW_VARYING_SIZE;
+ if (info->primitive_restart)
+ draw_flags |= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX;
+
/* For higher amounts of vertices (greater than what fits in a 16-bit
* short), the other value is needed, otherwise there will be bizarre
- * rendering artefacts. It's not clear what these values mean yet. */
+ * rendering artefacts. It's not clear what these values mean yet. This
+ * change is also needed for instancing and sometimes points (perhaps
+ * related to dynamically setting gl_PointSize) */
+
+ bool is_points = mode == PIPE_PRIM_POINTS;
+ bool many_verts = ctx->vertex_count > 0xFFFF;
+ bool instanced = ctx->instance_count > 1;
- draw_flags |= (mode == PIPE_PRIM_POINTS || ctx->vertex_count > 65535) ? 0x3000 : 0x18000;
+ draw_flags |= (is_points || many_verts || instanced) ? 0x3000 : 0x18000;
+
+ /* This doesn't make much sense */
+ if (mode == PIPE_PRIM_LINE_STRIP) {
+ draw_flags |= 0x800;
+ }
if (info->index_size) {
/* Calculate the min/max index used so we can figure out how
}
/* Use the corresponding values */
- invocation_count = max_index - min_index + 1;
+ vertex_count = max_index - min_index + 1;
ctx->payload_vertex.draw_start = min_index;
ctx->payload_tiler.draw_start = min_index;
ctx->payload_tiler.prefix.indices = (uintptr_t) NULL;
}
- ctx->payload_vertex.prefix.invocation_count = MALI_POSITIVE(invocation_count);
- ctx->payload_tiler.prefix.invocation_count = MALI_POSITIVE(invocation_count);
+ /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
+ * vertex_count, 1) */
+
+ panfrost_pack_work_groups_fused(
+ &ctx->payload_vertex.prefix,
+ &ctx->payload_tiler.prefix,
+ 1, vertex_count, info->instance_count,
+ 1, 1, 1);
+
ctx->payload_tiler.prefix.unknown_draw = draw_flags;
+ /* Encode the padded vertex count */
+
+ if (info->instance_count > 1) {
+ /* Triangles have non-even vertex counts so they change how
+ * padding works internally */
+
+ bool is_triangle =
+ mode == PIPE_PRIM_TRIANGLES ||
+ mode == PIPE_PRIM_TRIANGLE_STRIP ||
+ mode == PIPE_PRIM_TRIANGLE_FAN;
+
+ struct pan_shift_odd so =
+ panfrost_padded_vertex_count(vertex_count, !is_triangle);
+
+ ctx->payload_vertex.instance_shift = so.shift;
+ ctx->payload_tiler.instance_shift = so.shift;
+
+ ctx->payload_vertex.instance_odd = so.odd;
+ ctx->payload_tiler.instance_odd = so.odd;
+
+ ctx->padded_count = pan_expand_shift_odd(so);
+ } else {
+ ctx->padded_count = ctx->vertex_count;
+
+ /* Reset instancing state */
+ ctx->payload_vertex.instance_shift = 0;
+ ctx->payload_vertex.instance_odd = 0;
+ ctx->payload_tiler.instance_shift = 0;
+ ctx->payload_tiler.instance_odd = 0;
+ }
+
/* Fire off the draw itself */
panfrost_queue_draw(ctx);
}
/* Point sprites are emulated */
- if (ctx->rasterizer->base.sprite_coord_enable)
+ struct panfrost_shader_state *variant =
+ ctx->fs ? &ctx->fs->variants[ctx->fs->active_variant] : NULL;
+
+ if (ctx->rasterizer->base.sprite_coord_enable || (variant && variant->point_sprite_mask))
ctx->base.bind_fs_state(&ctx->base, ctx->fs);
}
panfrost_allocate_chunk(pan_context(pctx), 0, HEAP_DESCRIPTOR);
for (int i = 0; i < num_elements; ++i) {
- so->hw[i].index = elements[i].vertex_buffer_index;
+ so->hw[i].index = i;
enum pipe_format fmt = elements[i].src_format;
const struct util_format_description *desc = util_format_description(fmt);
},
.min_lod = FIXED_16(cso->min_lod),
.max_lod = FIXED_16(cso->max_lod),
- .unknown2 = 1,
+ .seamless_cube_map = cso->seamless_cube_map,
};
+ /* If necessary, we disable mipmapping in the sampler descriptor by
+ * clamping the LOD as tight as possible (from 0 to epsilon,
+ * essentially -- remember these are fixed point numbers, so
+ * epsilon=1/256) */
+
+ if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE)
+ sampler_descriptor.max_lod = sampler_descriptor.min_lod;
+
+ /* Enforce that there is something in the middle by adding epsilon*/
+
+ if (sampler_descriptor.min_lod == sampler_descriptor.max_lod)
+ sampler_descriptor.max_lod++;
+
+ /* Sanity check */
+ assert(sampler_descriptor.max_lod > sampler_descriptor.min_lod);
+
so->hw = sampler_descriptor;
return so;
struct panfrost_context *ctx = pan_context(pctx);
struct panfrost_constant_buffer *pbuf = &ctx->constant_buffer[shader];
- size_t sz = buf ? buf->buffer_size : 0;
+ util_copy_constant_buffer(&pbuf->cb[index], buf);
- /* Free previous buffer */
+ unsigned mask = (1 << index);
- pbuf->dirty = true;
- pbuf->size = sz;
-
- if (pbuf->buffer) {
- ralloc_free(pbuf->buffer);
- pbuf->buffer = NULL;
- }
-
- /* If unbinding, we're done */
-
- if (!buf)
- return;
-
- /* Multiple constant buffers not yet supported */
- assert(index == 0);
-
- const uint8_t *cpu;
-
- struct panfrost_resource *rsrc = (struct panfrost_resource *) (buf->buffer);
-
- if (rsrc) {
- cpu = rsrc->bo->cpu;
- } else if (buf->user_buffer) {
- cpu = buf->user_buffer;
- } else {
- DBG("No constant buffer?\n");
+ if (unlikely(!buf)) {
+ pbuf->enabled_mask &= ~mask;
+ pbuf->dirty_mask &= ~mask;
return;
}
- /* Copy the constant buffer into the driver context for later upload */
-
- pbuf->buffer = rzalloc_size(ctx, sz);
- memcpy(pbuf->buffer, cpu + buf->buffer_offset, sz);
+ pbuf->enabled_mask |= mask;
+ pbuf->dirty_mask |= mask;
}
static void
* (data) itself. So, we serialise the descriptor here and cache it for
* later. */
- /* Make sure it's something with which we're familiar */
- assert(bytes_per_pixel >= 1 && bytes_per_pixel <= 4);
-
/* TODO: Detect from format better */
const struct util_format_description *desc = util_format_description(prsrc->base.format);
unsigned usage2_layout = 0x10;
- switch (prsrc->bo->layout) {
+ switch (prsrc->layout) {
case PAN_AFBC:
usage2_layout |= 0x8 | 0x4;
break;
unsigned first_level = template->u.tex.first_level;
unsigned last_level = template->u.tex.last_level;
- if (prsrc->bo->layout == PAN_LINEAR) {
+ if (prsrc->layout == PAN_LINEAR) {
for (unsigned l = first_level; l <= last_level; ++l) {
- unsigned actual_stride = prsrc->bo->slices[l].stride;
+ unsigned actual_stride = prsrc->slices[l].stride;
unsigned width = u_minify(texture->width0, l);
unsigned comp_stride = width * bytes_per_pixel;
unsigned array_size = texture->array_size;
- if (texture->target == PIPE_TEXTURE_CUBE) {
+ if (template->target == PIPE_TEXTURE_CUBE) {
/* TODO: Cubemap arrays */
assert(array_size == 6);
+ array_size /= 6;
}
struct mali_texture_descriptor texture_descriptor = {
.format = format,
.srgb = desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB,
- .type = panfrost_translate_texture_type(texture->target),
+ .type = panfrost_translate_texture_type(template->target),
.usage2 = usage2_layout
},
.swizzle = panfrost_translate_swizzle_4(user_swizzle)
};
- //texture_descriptor.nr_mipmap_levels = last_level - first_level;
+ texture_descriptor.nr_mipmap_levels = last_level - first_level;
so->hw = texture_descriptor;
bool is_scanout = panfrost_is_scanout(ctx);
bool has_draws = job->last_job.gpu;
- if (!ctx->blitter->running && (!is_scanout || has_draws)) {
+ if (!ctx->wallpaper_batch && (!is_scanout || has_draws)) {
panfrost_flush(pctx, NULL, PIPE_FLUSH_END_OF_FRAME);
}
ctx->vt_framebuffer_mfbd = panfrost_emit_mfbd(ctx, ~0);
panfrost_attach_vt_framebuffer(ctx);
-
- struct panfrost_resource *tex = ((struct panfrost_resource *) ctx->pipe_framebuffer.cbufs[i]->texture);
- enum pipe_format format = ctx->pipe_framebuffer.cbufs[i]->format;
-
- bool can_afbc = panfrost_format_supports_afbc(format);
- bool is_scanout = panfrost_is_scanout(ctx);
-
- if (!is_scanout && tex->bo->layout != PAN_AFBC && can_afbc)
- panfrost_enable_afbc(ctx, tex, false);
-
- if (!is_scanout && !tex->bo->has_checksum)
- panfrost_enable_checksum(ctx, tex);
}
{
ctx->vt_framebuffer_mfbd = panfrost_emit_mfbd(ctx, ~0);
panfrost_attach_vt_framebuffer(ctx);
-
- struct panfrost_resource *tex = pan_resource(zb->texture);
- bool can_afbc = panfrost_format_supports_afbc(zb->format);
- bool is_scanout = panfrost_is_scanout(ctx);
-
- if (!is_scanout && tex->bo->layout != PAN_AFBC && can_afbc)
- panfrost_enable_afbc(ctx, tex, true);
}
}
}
if (panfrost->blitter)
util_blitter_destroy(panfrost->blitter);
+ if (panfrost->blitter_wallpaper)
+ util_blitter_destroy(panfrost->blitter_wallpaper);
+
panfrost_drm_free_slab(screen, &panfrost->scratchpad);
panfrost_drm_free_slab(screen, &panfrost->varying_mem);
panfrost_drm_free_slab(screen, &panfrost->shaders);
ctx->primconvert = util_primconvert_create(gallium, ctx->draw_modes);
ctx->blitter = util_blitter_create(gallium);
+ ctx->blitter_wallpaper = util_blitter_create(gallium);
+
assert(ctx->blitter);
+ assert(ctx->blitter_wallpaper);
/* Prepare for render! */
projects / mesa.git / blobdiff