#include "util/u_debug.h"
#include "util/u_memory.h"
-#include "util/u_format.h"
-#include "util/u_format_s3tc.h"
+#include "util/format/u_format.h"
+#include "util/format/u_format_s3tc.h"
#include "util/u_video.h"
#include "util/u_screen.h"
#include "util/os_time.h"
#include "pan_context.h"
#include "midgard/midgard_compile.h"
+#include "panfrost-quirks.h"
static const struct debug_named_value debug_options[] = {
{"msgs", PAN_DBG_MSGS, "Print debug messages"},
{"trace", PAN_DBG_TRACE, "Trace the command stream"},
{"deqp", PAN_DBG_DEQP, "Hacks for dEQP"},
{"afbc", PAN_DBG_AFBC, "Enable non-conformant AFBC impl"},
+ {"sync", PAN_DBG_SYNC, "Wait for each job's completion and check for any GPU fault"},
+ {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
DEBUG_NAMED_VALUE_END
};
static const char *
panfrost_get_name(struct pipe_screen *screen)
{
- return "panfrost";
+ return panfrost_model_name(pan_screen(screen)->gpu_id);
}
static const char *
panfrost_get_vendor(struct pipe_screen *screen)
{
- return "panfrost";
+ return "Panfrost";
}
static const char *
case PIPE_CAP_MAX_RENDER_TARGETS:
return is_deqp ? 4 : 1;
+ /* Throttling frames breaks pipelining */
+ case PIPE_CAP_THROTTLE:
+ return 0;
case PIPE_CAP_OCCLUSION_QUERY:
return 1;
case PIPE_CAP_TEXTURE_SWIZZLE:
return 1;
+ case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
+ case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
+ return 1;
+
case PIPE_CAP_TGSI_INSTANCEID:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
- return is_deqp ? 1 : 0;
+ return 1;
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
return is_deqp ? 4 : 0;
return 1;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
- return is_deqp ? 256 : 0; /* for GL3 */
+ return 256;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
return is_deqp ? 300 : 120;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
- return is_deqp ? 16 : 0;
+ return 16;
case PIPE_CAP_CUBE_MAP_ARRAY:
return is_deqp;
return (int)(system_memory >> 20);
}
+ case PIPE_CAP_SHADER_STENCIL_EXPORT:
+ return 1;
+
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
return 4;
case PIPE_CAP_MAX_VARYINGS:
return 16;
+ case PIPE_CAP_ALPHA_TEST:
+ case PIPE_CAP_FLATSHADE:
+ case PIPE_CAP_TWO_SIDED_COLOR:
+ case PIPE_CAP_CLIP_PLANES:
+ return 0;
+
default:
return u_pipe_screen_get_param_defaults(screen, param);
}
/* this is probably not totally correct.. but it's a start: */
switch (param) {
- case PIPE_SHADER_CAP_SCALAR_ISA:
- return 0;
-
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
return 16;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
- return shader == PIPE_SHADER_FRAGMENT ? 4 : 8;
+ return shader == PIPE_SHADER_FRAGMENT ? 4 : 16;
case PIPE_SHADER_CAP_MAX_TEMPS:
return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
return PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
- return (1 << PIPE_SHADER_IR_NIR);
+ return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
return 0;
default:
- fprintf(stderr, "unknown shader param %d\n", param);
+ DBG("unknown shader param %d\n", param);
return 0;
}
if (!format_desc)
return false;
- if (sample_count > 1)
+ /* MSAA 4x supported, but no more. Technically some revisions of the
+ * hardware can go up to 16x but we don't support higher modes yet. */
+
+ if (sample_count > 1 && !(pan_debug & PAN_DBG_DEQP))
+ return false;
+
+ if (sample_count > 4)
+ return false;
+
+ if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
return false;
/* Format wishlist */
if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
return false;
- if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN &&
- format_desc->layout != UTIL_FORMAT_LAYOUT_OTHER) {
- /* Compressed formats not yet hooked up. */
- return false;
+ switch (format_desc->layout) {
+ case UTIL_FORMAT_LAYOUT_PLAIN:
+ case UTIL_FORMAT_LAYOUT_OTHER:
+ break;
+ case UTIL_FORMAT_LAYOUT_ETC:
+ case UTIL_FORMAT_LAYOUT_ASTC:
+ return true;
+ default:
+ return false;
}
/* Internally, formats that are depth/stencil renderable are limited.
switch (param) {
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
- /* TODO: We'll want 64-bit pointers soon */
- RET((uint32_t []){ 32 });
+ RET((uint32_t []){ 64 });
case PIPE_COMPUTE_CAP_IR_TARGET:
if (ret)
{
struct panfrost_screen *screen = pan_screen(pscreen);
panfrost_bo_cache_evict_all(screen);
- pthread_mutex_destroy(&screen->bo_cache_lock);
+ pthread_mutex_destroy(&screen->bo_cache.lock);
+ pthread_mutex_destroy(&screen->active_bos_lock);
drmFreeVersion(screen->kernel_version);
ralloc_free(screen);
}
-static void
-panfrost_flush_frontbuffer(struct pipe_screen *_screen,
- struct pipe_resource *resource,
- unsigned level, unsigned layer,
- void *context_private,
- struct pipe_box *sub_box)
-{
- /* TODO: Display target integration */
-}
-
static uint64_t
panfrost_get_timestamp(struct pipe_screen *_screen)
{
return &midgard_nir_options;
}
-static unsigned
-panfrost_query_gpu_version(struct panfrost_screen *screen)
+static uint32_t
+panfrost_active_bos_hash(const void *key)
{
- struct drm_panfrost_get_param get_param = {0,};
- ASSERTED int ret;
+ const struct panfrost_bo *bo = key;
+
+ return _mesa_hash_data(&bo->gem_handle, sizeof(bo->gem_handle));
+}
- get_param.param = DRM_PANFROST_PARAM_GPU_PROD_ID;
- ret = drmIoctl(screen->fd, DRM_IOCTL_PANFROST_GET_PARAM, &get_param);
- assert(!ret);
+static bool
+panfrost_active_bos_cmp(const void *keya, const void *keyb)
+{
+ const struct panfrost_bo *a = keya, *b = keyb;
- return get_param.value;
+ return a->gem_handle == b->gem_handle;
}
struct pipe_screen *
if (ro) {
screen->ro = renderonly_dup(ro);
if (!screen->ro) {
- fprintf(stderr, "Failed to dup renderonly object\n");
+ DBG("Failed to dup renderonly object\n");
free(screen);
return NULL;
}
screen->fd = fd;
- screen->gpu_id = panfrost_query_gpu_version(screen);
- screen->require_sfbd = screen->gpu_id < 0x0750; /* T760 is the first to support MFBD */
+ screen->gpu_id = panfrost_query_gpu_version(screen->fd);
+ screen->core_count = panfrost_query_core_count(screen->fd);
+ screen->thread_tls_alloc = panfrost_query_thread_tls_alloc(screen->fd);
+ screen->quirks = panfrost_get_quirks(screen->gpu_id);
screen->kernel_version = drmGetVersion(fd);
/* Check if we're loading against a supported GPU model. */
switch (screen->gpu_id) {
+ case 0x720: /* T720 */
case 0x750: /* T760 */
case 0x820: /* T820 */
case 0x860: /* T860 */
break;
default:
/* Fail to load against untested models */
- debug_printf("panfrost: Unsupported model %X",
- screen->gpu_id);
+ debug_printf("panfrost: Unsupported model %X", screen->gpu_id);
return NULL;
}
- pthread_mutex_init(&screen->bo_cache_lock, NULL);
- for (unsigned i = 0; i < ARRAY_SIZE(screen->bo_cache); ++i)
- list_inithead(&screen->bo_cache[i]);
+ pthread_mutex_init(&screen->active_bos_lock, NULL);
+ screen->active_bos = _mesa_set_create(screen, panfrost_active_bos_hash,
+ panfrost_active_bos_cmp);
+
+ pthread_mutex_init(&screen->bo_cache.lock, NULL);
+ list_inithead(&screen->bo_cache.lru);
+ for (unsigned i = 0; i < ARRAY_SIZE(screen->bo_cache.buckets); ++i)
+ list_inithead(&screen->bo_cache.buckets[i]);
- if (pan_debug & PAN_DBG_TRACE)
- pandecode_initialize();
+ if (pan_debug & (PAN_DBG_TRACE | PAN_DBG_SYNC))
+ pandecode_initialize(!(pan_debug & PAN_DBG_TRACE));
screen->base.destroy = panfrost_destroy_screen;
screen->base.get_timestamp = panfrost_get_timestamp;
screen->base.is_format_supported = panfrost_is_format_supported;
screen->base.context_create = panfrost_create_context;
- screen->base.flush_frontbuffer = panfrost_flush_frontbuffer;
screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
screen->base.fence_reference = panfrost_fence_reference;
screen->base.fence_finish = panfrost_fence_finish;
+ screen->base.set_damage_region = panfrost_resource_set_damage_region;
panfrost_resource_screen_init(screen);