{"deqp", PAN_DBG_DEQP, "Hacks for dEQP"},
{"afbc", PAN_DBG_AFBC, "Enable non-conformant AFBC impl"},
{"sync", PAN_DBG_SYNC, "Wait for each job's completion and check for any GPU fault"},
+ {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
DEBUG_NAMED_VALUE_END
};
static const char *
panfrost_get_name(struct pipe_screen *screen)
{
- return "panfrost";
+ return panfrost_model_name(pan_screen(screen)->gpu_id);
}
static const char *
panfrost_get_vendor(struct pipe_screen *screen)
{
- return "panfrost";
+ return "Panfrost";
}
static const char *
case PIPE_CAP_TEXTURE_SWIZZLE:
return 1;
+ case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
+ case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
+ return 1;
+
case PIPE_CAP_TGSI_INSTANCEID:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
- return is_deqp ? 1 : 0;
+ return 1;
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
return is_deqp ? 4 : 0;
return 1;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
- return is_deqp ? 256 : 0; /* for GL3 */
+ return 256;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
return is_deqp ? 300 : 120;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
- return is_deqp ? 16 : 0;
+ return 16;
case PIPE_CAP_CUBE_MAP_ARRAY:
return is_deqp;
return 16;
case PIPE_CAP_ALPHA_TEST:
+ case PIPE_CAP_FLATSHADE:
+ case PIPE_CAP_TWO_SIDED_COLOR:
+ case PIPE_CAP_CLIP_PLANES:
return 0;
default:
return 16;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
- return shader == PIPE_SHADER_FRAGMENT ? 4 : 8;
+ return shader == PIPE_SHADER_FRAGMENT ? 4 : 16;
case PIPE_SHADER_CAP_MAX_TEMPS:
return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
if (!format_desc)
return false;
- if (sample_count > 1)
+ /* MSAA 4x supported, but no more. Technically some revisions of the
+ * hardware can go up to 16x but we don't support higher modes yet. */
+
+ if (sample_count > 1 && !(pan_debug & PAN_DBG_DEQP))
+ return false;
+
+ if (sample_count > 4)
+ return false;
+
+ if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
return false;
/* Format wishlist */
if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
return false;
- if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN &&
- format_desc->layout != UTIL_FORMAT_LAYOUT_OTHER) {
- /* Compressed formats not yet hooked up. */
- return false;
+ switch (format_desc->layout) {
+ case UTIL_FORMAT_LAYOUT_PLAIN:
+ case UTIL_FORMAT_LAYOUT_OTHER:
+ break;
+ case UTIL_FORMAT_LAYOUT_ETC:
+ case UTIL_FORMAT_LAYOUT_ASTC:
+ return true;
+ default:
+ return false;
}
/* Internally, formats that are depth/stencil renderable are limited.
return &midgard_nir_options;
}
-static __u64
-panfrost_query_raw(
- struct panfrost_screen *screen,
- enum drm_panfrost_param param,
- bool required)
-{
- struct drm_panfrost_get_param get_param = {0,};
- ASSERTED int ret;
-
- get_param.param = DRM_PANFROST_PARAM_GPU_PROD_ID;
- ret = drmIoctl(screen->fd, DRM_IOCTL_PANFROST_GET_PARAM, &get_param);
-
- assert(!(ret && required));
-
- return get_param.value;
-}
-
-static unsigned
-panfrost_query_gpu_version(struct panfrost_screen *screen)
-{
- return panfrost_query_raw(screen, DRM_PANFROST_PARAM_GPU_PROD_ID, true);
-}
-
static uint32_t
panfrost_active_bos_hash(const void *key)
{
screen->fd = fd;
- screen->gpu_id = panfrost_query_gpu_version(screen);
+ screen->gpu_id = panfrost_query_gpu_version(screen->fd);
+ screen->core_count = panfrost_query_core_count(screen->fd);
+ screen->thread_tls_alloc = panfrost_query_thread_tls_alloc(screen->fd);
screen->quirks = panfrost_get_quirks(screen->gpu_id);
screen->kernel_version = drmGetVersion(fd);