r300/compiler: Use variable lists in the rename_regs pass

[mesa.git] / src / gallium / drivers / r300 / compiler / radeon_opcodes.c

diff --git a/src/gallium/drivers/r300/compiler/radeon_opcodes.c b/src/gallium/drivers/r300/compiler/radeon_opcodes.c
index afd78ad79dd3963fd39ef14ec50dbd84479354ff..9bcb3c990adba0887b98997978a6fc2736884d2b 100644 (file)
--- a/src/gallium/drivers/r300/compiler/radeon_opcodes.c
+++ b/src/gallium/drivers/r300/compiler/radeon_opcodes.c
@@ -245,6 +245,13 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .HasDstReg = 1,
                .IsStandardScalar = 1
        },
+       {
+               .Opcode = RC_OPCODE_ROUND,
+               .Name = "ROUND",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1,
+               .IsComponentwise = 1
+       },
        {
                .Opcode = RC_OPCODE_RSQ,
                .Name = "RSQ",
@@ -430,6 +437,78 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
        {
                .Opcode = RC_OPCODE_KILP,
                .Name = "KILP",
+       },
+       {
+               .Opcode = RC_ME_PRED_SEQ,
+               .Name = "ME_PRED_SEQ",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_ME_PRED_SGT,
+               .Name = "ME_PRED_SGT",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_ME_PRED_SGE,
+               .Name = "ME_PRED_SGE",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_ME_PRED_SNEQ,
+               .Name = "ME_PRED_SNEQ",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_ME_PRED_SET_CLR,
+               .Name = "ME_PRED_SET_CLEAR",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_ME_PRED_SET_INV,
+               .Name = "ME_PRED_SET_INV",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_ME_PRED_SET_POP,
+               .Name = "ME_PRED_SET_POP",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_ME_PRED_SET_RESTORE,
+               .Name = "ME_PRED_SET_RESTORE",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_VE_PRED_SEQ_PUSH,
+               .Name = "VE_PRED_SEQ_PUSH",
+               .NumSrcRegs = 2,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_VE_PRED_SGT_PUSH,
+               .Name = "VE_PRED_SGT_PUSH",
+               .NumSrcRegs = 2,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_VE_PRED_SGE_PUSH,
+               .Name = "VE_PRED_SGE_PUSH",
+               .NumSrcRegs = 2,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_VE_PRED_SNEQ_PUSH,
+               .Name = "VE_PRED_SNEQ_PUSH",
+               .NumSrcRegs = 2,
+               .HasDstReg = 1
        }
 };
 
@@ -456,7 +535,7 @@ void rc_compute_sources_for_writemask(
                        srcmasks[src] |= writemask;
        } else if (opcode->IsStandardScalar) {
                for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src)
-                       srcmasks[src] |= RC_MASK_X;
+                       srcmasks[src] |= writemask;
        } else {
                switch(opcode->Opcode) {
                case RC_OPCODE_ARL: