gallium/drivers: Remove unnecessary semicolons

[mesa.git] / src / gallium / drivers / r300 / compiler / radeon_opcodes.c

diff --git a/src/gallium/drivers/r300/compiler/radeon_opcodes.c b/src/gallium/drivers/r300/compiler/radeon_opcodes.c
index 3b49ad7114c9743eb38ab3ad1a108b49548e118d..a251bbe45d0efab0e563383547b21261ae0163a9 100644 (file)
--- a/src/gallium/drivers/r300/compiler/radeon_opcodes.c
+++ b/src/gallium/drivers/r300/compiler/radeon_opcodes.c
@@ -59,6 +59,12 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .NumSrcRegs = 1,
                .HasDstReg = 1
        },
+       {
+               .Opcode = RC_OPCODE_ARR,
+               .Name = "ARR",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
        {
                .Opcode = RC_OPCODE_CEIL,
                .Name = "CEIL",
@@ -342,6 +348,13 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .HasDstReg = 1,
                .IsComponentwise = 1
        },
+       {
+               .Opcode = RC_OPCODE_TRUNC,
+               .Name = "TRUNC",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1,
+               .IsComponentwise = 1
+       },
        {
                .Opcode = RC_OPCODE_XPD,
                .Name = "XPD",
@@ -437,6 +450,78 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
        {
                .Opcode = RC_OPCODE_KILP,
                .Name = "KILP",
+       },
+       {
+               .Opcode = RC_ME_PRED_SEQ,
+               .Name = "ME_PRED_SEQ",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_ME_PRED_SGT,
+               .Name = "ME_PRED_SGT",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_ME_PRED_SGE,
+               .Name = "ME_PRED_SGE",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_ME_PRED_SNEQ,
+               .Name = "ME_PRED_SNEQ",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_ME_PRED_SET_CLR,
+               .Name = "ME_PRED_SET_CLEAR",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_ME_PRED_SET_INV,
+               .Name = "ME_PRED_SET_INV",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_ME_PRED_SET_POP,
+               .Name = "ME_PRED_SET_POP",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_ME_PRED_SET_RESTORE,
+               .Name = "ME_PRED_SET_RESTORE",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_VE_PRED_SEQ_PUSH,
+               .Name = "VE_PRED_SEQ_PUSH",
+               .NumSrcRegs = 2,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_VE_PRED_SGT_PUSH,
+               .Name = "VE_PRED_SGT_PUSH",
+               .NumSrcRegs = 2,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_VE_PRED_SGE_PUSH,
+               .Name = "VE_PRED_SGE_PUSH",
+               .NumSrcRegs = 2,
+               .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_VE_PRED_SNEQ_PUSH,
+               .Name = "VE_PRED_SNEQ_PUSH",
+               .NumSrcRegs = 2,
+               .HasDstReg = 1
        }
 };
 
@@ -467,6 +552,7 @@ void rc_compute_sources_for_writemask(
        } else {
                switch(opcode->Opcode) {
                case RC_OPCODE_ARL:
+               case RC_OPCODE_ARR:
                        srcmasks[0] |= RC_MASK_X;
                        break;
                case RC_OPCODE_DP2: