freedreno/a3xx: add blend state

[mesa.git] / src / gallium / drivers / r300 / r300_flush.c

diff --git a/src/gallium/drivers/r300/r300_flush.c b/src/gallium/drivers/r300/r300_flush.c
index 365dc8c3c11ff53723b4ce1a43a153494ed300b0..3dd3864353c9000446584b78d9b4af7996ded532 100644 (file)
--- a/src/gallium/drivers/r300/r300_flush.c
+++ b/src/gallium/drivers/r300/r300_flush.c
@@ -43,8 +43,16 @@ static void r300_flush_and_cleanup(struct r300_context *r300, unsigned flags)
     if (r300->screen->caps.is_r500)
         r500_emit_index_bias(r300, 0);
 
+    /* The DDX doesn't set these regs. */
+    if (r300->screen->info.drm_minor >= 6) {
+        CS_LOCALS(r300);
+        OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
+        OUT_CS(0x66666666);
+        OUT_CS(0x6666666);
+    }
+
     r300->flush_counter++;
-    r300->rws->cs_flush(r300->cs, flags);
+    r300->rws->cs_flush(r300->cs, flags, 0);
     r300->dirty_hw = 0;
 
     /* New kitchen sink, baby. */
@@ -92,11 +100,11 @@ void r300_flush(struct pipe_context *pipe,
              * and we cannot emit an empty CS. Let's write to some reg. */
             CS_LOCALS(r300);
             OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0);
-            r300->rws->cs_flush(r300->cs, flags);
+            r300->rws->cs_flush(r300->cs, flags, 0);
         } else {
             /* Even if hw is not dirty, we should at least reset the CS in case
              * the space checking failed for the first draw operation. */
-            r300->rws->cs_flush(r300->cs, flags);
+            r300->rws->cs_flush(r300->cs, flags, 0);
         }
     }
 
@@ -131,7 +139,7 @@ void r300_flush(struct pipe_context *pipe,
 
 static void r300_flush_wrapped(struct pipe_context *pipe,
                                struct pipe_fence_handle **fence,
-                               enum pipe_flush_flags flags)
+                               unsigned flags)
 {
     r300_flush(pipe,
                flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0,