r500_emit_index_bias(r300, 0);
/* The DDX doesn't set these regs. */
- if (r300->screen->info.drm_minor >= 6) {
+ {
CS_LOCALS(r300);
OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
OUT_CS(0x66666666);
}
r300->flush_counter++;
- r300->rws->cs_flush(r300->cs, flags, fence, 0);
+ r300->rws->cs_flush(r300->cs, flags, fence);
r300->dirty_hw = 0;
/* New kitchen sink, baby. */
{
struct r300_context *r300 = r300_context(pipe);
- if (r300->screen->info.drm_minor >= 12) {
- flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
- }
-
if (r300->dirty_hw) {
r300_flush_and_cleanup(r300, flags, fence);
} else {
* and we cannot emit an empty CS. Let's write to some reg. */
CS_LOCALS(r300);
OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0);
- r300->rws->cs_flush(r300->cs, flags, fence, 0);
+ r300->rws->cs_flush(r300->cs, flags, fence);
} else {
/* Even if hw is not dirty, we should at least reset the CS in case
* the space checking failed for the first draw operation. */
- r300->rws->cs_flush(r300->cs, flags, NULL, 0);
+ r300->rws->cs_flush(r300->cs, flags, NULL);
}
}