r600g: on evergreen the centroid isn't set in this register.

[mesa.git] / src / gallium / drivers / r600 / eg_hw_states.c

diff --git a/src/gallium/drivers/r600/eg_hw_states.c b/src/gallium/drivers/r600/eg_hw_states.c
index 6e823689847ab2f885ed672348d262f595124fcf..ebbc9c3f37513edfe75e80ab5655064ed349e773 100644 (file)
--- a/src/gallium/drivers/r600/eg_hw_states.c
+++ b/src/gallium/drivers/r600/eg_hw_states.c
@@ -200,6 +200,7 @@ static void eg_rasterizer(struct r600_context *rctx, struct radeon_state *rstate
        unsigned offset_db_fmt_cntl = 0;
        unsigned tmp;
        unsigned prov_vtx = 1;
+       unsigned polygon_dual_mode;
 
        if (rctx->clip)
                clip = &rctx->clip->state.clip;
@@ -254,6 +255,9 @@ static void eg_rasterizer(struct r600_context *rctx, struct radeon_state *rstate
                rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
                rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
        }
+       polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
+                            state->fill_back != PIPE_POLYGON_MODE_FILL);
+
        rstate->states[EG_RASTERIZER__PA_SU_SC_MODE_CNTL] =
                S_028814_PROVOKING_VTX_LAST(prov_vtx) |
                S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
@@ -261,7 +265,10 @@ static void eg_rasterizer(struct r600_context *rctx, struct radeon_state *rstate
                S_028814_FACE(!state->front_ccw) |
                S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
                S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
-               S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
+               S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
+               S_028814_POLY_MODE(polygon_dual_mode) |
+               S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
+               S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
        rstate->states[EG_RASTERIZER__PA_CL_VS_OUT_CNTL] =
                        S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
                        S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
@@ -357,6 +364,7 @@ static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
        struct r600_screen *rscreen = rctx->screen;
        unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
        unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
+       unsigned db_count_control = 0;
        struct r600_shader *rshader;
        struct r600_query *rquery = NULL;
        boolean query_running;
@@ -418,9 +426,9 @@ static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
        db_render_control = 0;
 ///    db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
 ///            S_028D0C_DEPTH_COMPRESS_DISABLE(1);
-       db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
-               S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
-               S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
+       db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
+               S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
+               S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
 
        query_running = FALSE;
 
@@ -431,8 +439,8 @@ static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
        }
 
        if (query_running) {
-               db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
-               db_render_control |= S_028D0C_PERFECT_ZPASS_COUNTS(1);
+               db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
+               db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
        }
 
        rstate->states[EG_DSA__DB_STENCIL_CLEAR] = 0x00000000;
@@ -448,7 +456,7 @@ static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
        rstate->states[EG_DSA__DB_SHADER_CONTROL] = db_shader_control;
        rstate->states[EG_DSA__DB_RENDER_CONTROL] = db_render_control;
        rstate->states[EG_DSA__DB_RENDER_OVERRIDE] = db_render_override;
-         
+       rstate->states[EG_DSA__DB_COUNT_CONTROL] = db_count_control;
        rstate->states[EG_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
        rstate->states[EG_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
        rstate->states[EG_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
@@ -522,7 +530,6 @@ static void eg_resource(struct pipe_context *ctx, struct radeon_state *rstate,
        unsigned format;
        uint32_t word4 = 0, yuv_format = 0, pitch = 0;
        unsigned char swizzle[4];
-       int r;
 
        rstate->cpm4 = 0;
        swizzle[0] = view->swizzle_r;
@@ -910,7 +917,7 @@ static int eg_draw_vgt_prim(struct r600_draw *draw,
        draw->vgt.states[EG_VGT__VGT_PRIMITIVE_TYPE] = prim;
        draw->vgt.states[EG_VGT__VGT_MAX_VTX_INDX] = draw->max_index;
        draw->vgt.states[EG_VGT__VGT_MIN_VTX_INDX] = draw->min_index;
-       draw->vgt.states[EG_VGT__VGT_INDX_OFFSET] = draw->start;
+       draw->vgt.states[EG_VGT__VGT_INDX_OFFSET] = draw->index_bias;
        draw->vgt.states[EG_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
        draw->vgt.states[EG_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
        draw->vgt.states[EG_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
@@ -935,7 +942,6 @@ static int eg_ps_shader(struct r600_context *rctx, struct r600_context_state *rp
        radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
        for (i = 0; i < rshader->ninput; i++) {
                tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(rctx, rshader, i));
-               tmp |= S_028644_SEL_CENTROID(1);
                if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
                        have_pos = TRUE;
                if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||