r600: Lower lerp after tgsi_to_nir

[mesa.git] / src / gallium / drivers / r600 / evergreen_compute.c

diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c
index 9085be4e2f33c0077b741bdafc032795e015110d..98d4b97d7fc00014d5bf78761ae8a00f0a842299 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -84,6 +84,25 @@ writable images will consume TEX slots, VTX slots too because of linear indexing
 
 */
 
+#ifdef HAVE_OPENCL
+static void radeon_shader_binary_init(struct r600_shader_binary *b)
+{
+       memset(b, 0, sizeof(*b));
+}
+
+static void radeon_shader_binary_clean(struct r600_shader_binary *b)
+{
+       if (!b)
+               return;
+       FREE(b->code);
+       FREE(b->config);
+       FREE(b->rodata);
+       FREE(b->global_symbol_offsets);
+       FREE(b->relocs);
+       FREE(b->disasm_string);
+}
+#endif
+
 struct r600_resource *r600_compute_buffer_alloc_vram(struct r600_screen *screen,
                                                     unsigned size)
 {
@@ -186,7 +205,7 @@ static void evergreen_cs_set_constant_buffer(struct r600_context *rctx,
 #ifdef HAVE_OPENCL
 static void parse_symbol_table(Elf_Data *symbol_table_data,
                                const GElf_Shdr *symbol_table_header,
-                               struct ac_shader_binary *binary)
+                               struct r600_shader_binary *binary)
 {
        GElf_Sym symbol;
        unsigned i = 0;
@@ -230,7 +249,7 @@ static void parse_symbol_table(Elf_Data *symbol_table_data,
 
 static void parse_relocs(Elf *elf, Elf_Data *relocs, Elf_Data *symbols,
                        unsigned symbol_sh_link,
-                       struct ac_shader_binary *binary)
+                       struct r600_shader_binary *binary)
 {
        unsigned i;
 
@@ -238,12 +257,12 @@ static void parse_relocs(Elf *elf, Elf_Data *relocs, Elf_Data *symbols,
                return;
        }
        binary->relocs = CALLOC(binary->reloc_count,
-                       sizeof(struct ac_shader_reloc));
+                       sizeof(struct r600_shader_reloc));
        for (i = 0; i < binary->reloc_count; i++) {
                GElf_Sym symbol;
                GElf_Rel rel;
                char *symbol_name;
-               struct ac_shader_reloc *reloc = &binary->relocs[i];
+               struct r600_shader_reloc *reloc = &binary->relocs[i];
 
                gelf_getrel(relocs, i, &rel);
                gelf_getsym(symbols, GELF_R_SYM(rel.r_info), &symbol);
@@ -256,7 +275,7 @@ static void parse_relocs(Elf *elf, Elf_Data *relocs, Elf_Data *symbols,
 }
 
 static void r600_elf_read(const char *elf_data, unsigned elf_size,
-                struct ac_shader_binary *binary)
+                struct r600_shader_binary *binary)
 {
        char *elf_buffer;
        Elf *elf;
@@ -335,7 +354,7 @@ static void r600_elf_read(const char *elf_data, unsigned elf_size,
 }
 
 static const unsigned char *r600_shader_binary_config_start(
-       const struct ac_shader_binary *binary,
+       const struct r600_shader_binary *binary,
        uint64_t symbol_offset)
 {
        unsigned i;
@@ -348,7 +367,7 @@ static const unsigned char *r600_shader_binary_config_start(
        return binary->config;
 }
 
-static void r600_shader_binary_read_config(const struct ac_shader_binary *binary,
+static void r600_shader_binary_read_config(const struct r600_shader_binary *binary,
                                           struct r600_bytecode *bc,
                                           uint64_t symbol_offset,
                                           boolean *use_kill)
@@ -384,7 +403,7 @@ static void r600_shader_binary_read_config(const struct ac_shader_binary *binary
 }
 
 static unsigned r600_create_shader(struct r600_bytecode *bc,
-                                  const struct ac_shader_binary *binary,
+                                  const struct r600_shader_binary *binary,
                                   boolean *use_kill)
 
 {
@@ -410,8 +429,7 @@ static void *evergreen_create_compute_state(struct pipe_context *ctx,
        struct r600_context *rctx = (struct r600_context *)ctx;
        struct r600_pipe_compute *shader = CALLOC_STRUCT(r600_pipe_compute);
 #ifdef HAVE_OPENCL
-       const struct pipe_llvm_program_header *header;
-       const char *code;
+       const struct pipe_binary_program_header *header;
        void *p;
        boolean use_kill;
 #endif
@@ -423,16 +441,16 @@ static void *evergreen_create_compute_state(struct pipe_context *ctx,
 
        shader->ir_type = cso->ir_type;
 
-       if (shader->ir_type == PIPE_SHADER_IR_TGSI) {
-               shader->sel = r600_create_shader_state_tokens(ctx, cso->prog, PIPE_SHADER_COMPUTE);
+       if (shader->ir_type == PIPE_SHADER_IR_TGSI ||
+           shader->ir_type == PIPE_SHADER_IR_NIR) {
+               shader->sel = r600_create_shader_state_tokens(ctx, cso->prog, cso->ir_type, PIPE_SHADER_COMPUTE);
                return shader;
        }
 #ifdef HAVE_OPENCL
        COMPUTE_DBG(rctx->screen, "*** evergreen_create_compute_state\n");
        header = cso->prog;
-       code = cso->prog + sizeof(struct pipe_llvm_program_header);
        radeon_shader_binary_init(&shader->binary);
-       r600_elf_read(code, header->num_bytes, &shader->binary);
+       r600_elf_read(header->blob, header->num_bytes, &shader->binary);
        r600_create_shader(&shader->bc, &shader->binary, &use_kill);
 
        /* Upload code + ROdata */
@@ -459,13 +477,14 @@ static void evergreen_delete_compute_state(struct pipe_context *ctx, void *state
        if (!shader)
                return;
 
-       if (shader->ir_type == PIPE_SHADER_IR_TGSI) {
+       if (shader->ir_type == PIPE_SHADER_IR_TGSI ||
+           shader->ir_type == PIPE_SHADER_IR_NIR) {
                r600_delete_shader_selector(ctx, shader->sel);
        } else {
 #ifdef HAVE_OPENCL
                radeon_shader_binary_clean(&shader->binary);
-               pipe_resource_reference(&shader->code_bo, NULL);
-               pipe_resource_reference(&shader->kernel_param, NULL);
+               pipe_resource_reference((struct pipe_resource**)&shader->code_bo, NULL);
+               pipe_resource_reference((struct pipe_resource**)&shader->kernel_param, NULL);
 #endif
                r600_destroy_shader(&shader->bc);
        }
@@ -483,12 +502,14 @@ static void evergreen_bind_compute_state(struct pipe_context *ctx, void *state)
                return;
        }
 
-       if (cstate->ir_type == PIPE_SHADER_IR_TGSI) {
+       if (cstate->ir_type == PIPE_SHADER_IR_TGSI ||
+           cstate->ir_type == PIPE_SHADER_IR_NIR) {
                bool compute_dirty;
-
-               r600_shader_select(ctx, cstate->sel, &compute_dirty);
+               cstate->sel->ir_type = cstate->ir_type;
+               if (r600_shader_select(ctx, cstate->sel, &compute_dirty))
+                       R600_ERR("Failed to select compute shader\n");
        }
-
+       
        rctx->cs_shader_state.shader = (struct r600_pipe_compute *)state;
 }
 
@@ -587,9 +608,10 @@ static void evergreen_emit_dispatch(struct r600_context *rctx,
        int grid_size = 1;
        unsigned lds_size = shader->local_size / 4;
 
-       if (shader->ir_type != PIPE_SHADER_IR_TGSI)
+       if (shader->ir_type != PIPE_SHADER_IR_TGSI &&
+           shader->ir_type != PIPE_SHADER_IR_NIR)
                lds_size += shader->bc.nlds_dw;
-
+       
        /* Calculate group_size/grid_size */
        for (i = 0; i < 3; i++) {
                group_size *= info->block[i];
@@ -717,8 +739,13 @@ static void compute_emit_cs(struct r600_context *rctx,
                rctx->cmd_buf_is_compute = true;
        }
 
-       if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI) {
-               r600_shader_select(&rctx->b.b, rctx->cs_shader_state.shader->sel, &compute_dirty);
+       if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI||
+           rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_NIR) {
+               if (r600_shader_select(&rctx->b.b, rctx->cs_shader_state.shader->sel, &compute_dirty)) {
+                       R600_ERR("Failed to select compute shader\n");
+                       return;
+               }
+               
                current = rctx->cs_shader_state.shader->sel->current;
                if (compute_dirty) {
                        rctx->cs_shader_state.atom.num_dw = current->command_buffer.num_dw;
@@ -769,7 +796,8 @@ static void compute_emit_cs(struct r600_context *rctx,
 
        /* emit config state */
        if (rctx->b.chip_class == EVERGREEN) {
-               if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI) {
+               if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI||
+                   rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_NIR) {
                        radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
                        radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
                        radeon_emit(cs, 0);
@@ -782,7 +810,8 @@ static void compute_emit_cs(struct r600_context *rctx,
        rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
        r600_flush_emit(rctx);
 
-       if (rctx->cs_shader_state.shader->ir_type != PIPE_SHADER_IR_TGSI) {
+       if (rctx->cs_shader_state.shader->ir_type != PIPE_SHADER_IR_TGSI &&
+           rctx->cs_shader_state.shader->ir_type != PIPE_SHADER_IR_NIR) {
 
                compute_setup_cbs(rctx);
 
@@ -838,7 +867,8 @@ static void compute_emit_cs(struct r600_context *rctx,
                radeon_emit(cs, PKT3C(PKT3_DEALLOC_STATE, 0, 0));
                radeon_emit(cs, 0);
        }
-       if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI)
+       if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI ||
+           rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_NIR)
                evergreen_emit_atomic_buffer_save(rctx, true, combined_atomics, &atomic_used_mask);
 
 #if 0
@@ -865,7 +895,8 @@ void evergreen_emit_cs_shader(struct r600_context *rctx,
        struct r600_resource *code_bo;
        unsigned ngpr, nstack;
 
-       if (shader->ir_type == PIPE_SHADER_IR_TGSI) {
+       if (shader->ir_type == PIPE_SHADER_IR_TGSI ||
+           shader->ir_type == PIPE_SHADER_IR_NIR) {
                code_bo = shader->sel->current->bo;
                va = shader->sel->current->bo->gpu_address;
                ngpr = shader->sel->current->shader.bc.ngpr;
@@ -899,7 +930,8 @@ static void evergreen_launch_grid(struct pipe_context *ctx,
        struct r600_pipe_compute *shader = rctx->cs_shader_state.shader;
        boolean use_kill;
 
-       if (shader->ir_type != PIPE_SHADER_IR_TGSI) {
+       if (shader->ir_type != PIPE_SHADER_IR_TGSI &&
+           shader->ir_type != PIPE_SHADER_IR_NIR) {
                rctx->cs_shader_state.pc = info->pc;
                /* Get the config information for this kernel. */
                r600_shader_binary_read_config(&shader->binary, &shader->bc,