#include "evergreen_compute.h"
#include "evergreen_compute_internal.h"
#include "compute_memory_pool.h"
+#include "sb/sb_public.h"
#ifdef HAVE_OPENCL
#include "radeon_llvm_util.h"
#endif
*/
+struct r600_resource* r600_compute_buffer_alloc_vram(
+ struct r600_screen *screen,
+ unsigned size)
+{
+ struct pipe_resource * buffer = NULL;
+ assert(size);
+
+ buffer = pipe_buffer_create(
+ (struct pipe_screen*) screen,
+ PIPE_BIND_CUSTOM,
+ PIPE_USAGE_IMMUTABLE,
+ size);
+
+ return (struct r600_resource *)buffer;
+}
+
+
+static void evergreen_set_rat(
+ struct r600_pipe_compute *pipe,
+ int id,
+ struct r600_resource* bo,
+ int start,
+ int size)
+{
+ struct pipe_surface rat_templ;
+ struct r600_surface *surf = NULL;
+ struct r600_context *rctx = NULL;
+
+ assert(id < 12);
+ assert((size & 3) == 0);
+ assert((start & 0xFF) == 0);
+
+ rctx = pipe->ctx;
+
+ COMPUTE_DBG(rctx->screen, "bind rat: %i \n", id);
+
+ /* Create the RAT surface */
+ memset(&rat_templ, 0, sizeof(rat_templ));
+ rat_templ.format = PIPE_FORMAT_R32_UINT;
+ rat_templ.u.tex.level = 0;
+ rat_templ.u.tex.first_layer = 0;
+ rat_templ.u.tex.last_layer = 0;
+
+ /* Add the RAT the list of color buffers */
+ pipe->ctx->framebuffer.state.cbufs[id] = pipe->ctx->b.b.create_surface(
+ (struct pipe_context *)pipe->ctx,
+ (struct pipe_resource *)bo, &rat_templ);
+
+ /* Update the number of color buffers */
+ pipe->ctx->framebuffer.state.nr_cbufs =
+ MAX2(id + 1, pipe->ctx->framebuffer.state.nr_cbufs);
+
+ /* Update the cb_target_mask
+ * XXX: I think this is a potential spot for bugs once we start doing
+ * GL interop. cb_target_mask may be modified in the 3D sections
+ * of this driver. */
+ pipe->ctx->compute_cb_target_mask |= (0xf << (id * 4));
+
+ surf = (struct r600_surface*)pipe->ctx->framebuffer.state.cbufs[id];
+ evergreen_init_color_surface_rat(rctx, surf);
+}
+
static void evergreen_cs_set_vertex_buffer(
struct r600_context * rctx,
unsigned vb_index,
/* The vertex instructions in the compute shaders use the texture cache,
* so we need to invalidate it. */
- rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
+ rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
state->enabled_mask |= 1 << vb_index;
state->dirty_mask |= 1 << vb_index;
state->atom.dirty = true;
cb.buffer = buffer;
cb.user_buffer = NULL;
- rctx->context.set_constant_buffer(&rctx->context, PIPE_SHADER_COMPUTE, cb_index, &cb);
+ rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_COMPUTE, cb_index, &cb);
}
static const struct u_resource_vtbl r600_global_buffer_vtbl =
#endif
shader->ctx = (struct r600_context*)ctx;
- shader->resources = (struct evergreen_compute_resource*)
- CALLOC(sizeof(struct evergreen_compute_resource),
- get_compute_resource_num());
- shader->local_size = cso->req_local_mem; ///TODO: assert it
+ shader->local_size = cso->req_local_mem;
shader->private_size = cso->req_private_mem;
shader->input_size = cso->req_input_mem;
{
struct r600_pipe_compute *shader = (struct r600_pipe_compute *)state;
- free(shader->resources);
free(shader);
}
uint32_t * global_size_start;
uint32_t * local_size_start;
uint32_t * kernel_parameters_start;
+ struct pipe_box box;
+ struct pipe_transfer *transfer = NULL;
if (shader->input_size == 0) {
return;
if (!shader->kernel_param) {
/* Add space for the grid dimensions */
- shader->kernel_param = r600_compute_buffer_alloc_vram(
- ctx->screen, input_size);
+ shader->kernel_param = (struct r600_resource *)
+ pipe_buffer_create(ctx_->screen, PIPE_BIND_CUSTOM,
+ PIPE_USAGE_IMMUTABLE, input_size);
}
- num_work_groups_start = r600_buffer_mmap_sync_with_rings(ctx, shader->kernel_param, PIPE_TRANSFER_WRITE);
+ u_box_1d(0, input_size, &box);
+ num_work_groups_start = ctx_->transfer_map(ctx_,
+ (struct pipe_resource*)shader->kernel_param,
+ 0, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_DISCARD_RANGE,
+ &box, &transfer);
global_size_start = num_work_groups_start + (3 * (sizeof(uint) /4));
local_size_start = global_size_start + (3 * (sizeof(uint)) / 4);
kernel_parameters_start = local_size_start + (3 * (sizeof(uint)) / 4);
((unsigned*)num_work_groups_start)[i]);
}
- ctx->ws->buffer_unmap(shader->kernel_param->cs_buf);
+ ctx_->transfer_unmap(ctx_, transfer);
/* ID=0 is reserved for the parameters */
evergreen_cs_set_constant_buffer(ctx, 0, 0, input_size,
const uint *block_layout, const uint *grid_layout)
{
int i;
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+ struct r600_pipe_compute *shader = rctx->cs_shader_state.shader;
unsigned num_waves;
- unsigned num_pipes = rctx->screen->info.r600_max_pipes;
+ unsigned num_pipes = rctx->screen->b.info.r600_max_pipes;
unsigned wave_divisor = (16 * num_pipes);
int group_size = 1;
int grid_size = 1;
- /* XXX: Enable lds and get size from cs_shader_state */
- unsigned lds_size = 0;
+ unsigned lds_size = shader->local_size / 4 + shader->active_kernel->bc.nlds_dw;
/* Calculate group_size/grid_size */
for (i = 0; i < 3; i++) {
num_waves = (block_layout[0] * block_layout[1] * block_layout[2] +
wave_divisor - 1) / wave_divisor;
- COMPUTE_DBG(rctx->screen, "Using %u pipes, there are %u wavefronts per thread block\n",
- num_pipes, num_waves);
-
- /* XXX: Partition the LDS between PS/CS. By default half (4096 dwords
- * on Evergreen) oes to Pixel Shaders and half goes to Compute Shaders.
- * We may need to allocat the entire LDS space for Compute Shaders.
- *
- * EG: R_008E2C_SQ_LDS_RESOURCE_MGMT := S_008E2C_NUM_LS_LDS(lds_dwords)
- * CM: CM_R_0286FC_SPI_LDS_MGMT := S_0286FC_NUM_LS_LDS(lds_dwords)
- */
+ COMPUTE_DBG(rctx->screen, "Using %u pipes, "
+ "%u wavefronts per thread block, "
+ "allocating %u dwords lds.\n",
+ num_pipes, num_waves, lds_size);
r600_write_config_reg(cs, R_008970_VGT_NUM_INDICES, group_size);
r600_write_config_reg_seq(cs, R_00899C_VGT_COMPUTE_START_X, 3);
- r600_write_value(cs, 0); /* R_00899C_VGT_COMPUTE_START_X */
- r600_write_value(cs, 0); /* R_0089A0_VGT_COMPUTE_START_Y */
- r600_write_value(cs, 0); /* R_0089A4_VGT_COMPUTE_START_Z */
+ radeon_emit(cs, 0); /* R_00899C_VGT_COMPUTE_START_X */
+ radeon_emit(cs, 0); /* R_0089A0_VGT_COMPUTE_START_Y */
+ radeon_emit(cs, 0); /* R_0089A4_VGT_COMPUTE_START_Z */
r600_write_config_reg(cs, R_0089AC_VGT_COMPUTE_THREAD_GROUP_SIZE,
group_size);
r600_write_compute_context_reg_seq(cs, R_0286EC_SPI_COMPUTE_NUM_THREAD_X, 3);
- r600_write_value(cs, block_layout[0]); /* R_0286EC_SPI_COMPUTE_NUM_THREAD_X */
- r600_write_value(cs, block_layout[1]); /* R_0286F0_SPI_COMPUTE_NUM_THREAD_Y */
- r600_write_value(cs, block_layout[2]); /* R_0286F4_SPI_COMPUTE_NUM_THREAD_Z */
+ radeon_emit(cs, block_layout[0]); /* R_0286EC_SPI_COMPUTE_NUM_THREAD_X */
+ radeon_emit(cs, block_layout[1]); /* R_0286F0_SPI_COMPUTE_NUM_THREAD_Y */
+ radeon_emit(cs, block_layout[2]); /* R_0286F4_SPI_COMPUTE_NUM_THREAD_Z */
+
+ if (rctx->b.chip_class < CAYMAN) {
+ assert(lds_size <= 8192);
+ } else {
+ /* Cayman appears to have a slightly smaller limit, see the
+ * value of CM_R_0286FC_SPI_LDS_MGMT.NUM_LS_LDS */
+ assert(lds_size <= 8160);
+ }
r600_write_compute_context_reg(cs, CM_R_0288E8_SQ_LDS_ALLOC,
lds_size | (num_waves << 14));
/* Dispatch packet */
- r600_write_value(cs, PKT3C(PKT3_DISPATCH_DIRECT, 3, 0));
- r600_write_value(cs, grid_layout[0]);
- r600_write_value(cs, grid_layout[1]);
- r600_write_value(cs, grid_layout[2]);
+ radeon_emit(cs, PKT3C(PKT3_DISPATCH_DIRECT, 3, 0));
+ radeon_emit(cs, grid_layout[0]);
+ radeon_emit(cs, grid_layout[1]);
+ radeon_emit(cs, grid_layout[2]);
/* VGT_DISPATCH_INITIATOR = COMPUTE_SHADER_EN */
- r600_write_value(cs, 1);
+ radeon_emit(cs, 1);
}
static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout,
const uint *grid_layout)
{
- struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
unsigned flush_flags = 0;
int i;
- struct evergreen_compute_resource *resources =
- ctx->cs_shader_state.shader->resources;
/* make sure that the gfx ring is only one active */
- if (ctx->rings.dma.cs) {
- ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+ if (ctx->b.rings.dma.cs) {
+ ctx->b.rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
}
/* Initialize all the compute-related registers.
*/
r600_emit_command_buffer(cs, &ctx->start_compute_cs_cmd);
- ctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
+ ctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
r600_flush_emit(ctx);
/* Emit colorbuffers. */
- for (i = 0; i < ctx->framebuffer.state.nr_cbufs; i++) {
+ /* XXX support more than 8 colorbuffers (the offsets are not a multiple of 0x3C for CB8-11) */
+ for (i = 0; i < 8 && i < ctx->framebuffer.state.nr_cbufs; i++) {
struct r600_surface *cb = (struct r600_surface*)ctx->framebuffer.state.cbufs[i];
- unsigned reloc = r600_context_bo_reloc(ctx, &ctx->rings.gfx,
+ unsigned reloc = r600_context_bo_reloc(&ctx->b, &ctx->b.rings.gfx,
(struct r600_resource*)cb->base.texture,
RADEON_USAGE_READWRITE);
r600_write_compute_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 7);
- r600_write_value(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
- r600_write_value(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
- r600_write_value(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
- r600_write_value(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
- r600_write_value(cs, cb->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
- r600_write_value(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
- r600_write_value(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
+ radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
+ radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
+ radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
+ radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
+ radeon_emit(cs, cb->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
+ radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
+ radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
- r600_write_value(cs, reloc);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
+ radeon_emit(cs, reloc);
if (!ctx->keep_tiling_flags) {
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
- r600_write_value(cs, reloc);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
+ radeon_emit(cs, reloc);
}
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
- r600_write_value(cs, reloc);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
+ radeon_emit(cs, reloc);
+ }
+ if (ctx->keep_tiling_flags) {
+ for (; i < 8 ; i++) {
+ r600_write_compute_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
+ S_028C70_FORMAT(V_028C70_COLOR_INVALID));
+ }
+ for (; i < 12; i++) {
+ r600_write_compute_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C,
+ S_028C70_FORMAT(V_028C70_COLOR_INVALID));
+ }
}
/* Set CB_TARGET_MASK XXX: Use cb_misc_state */
/* Emit compute shader state */
r600_emit_atom(ctx, &ctx->cs_shader_state.atom);
- for (i = 0; i < get_compute_resource_num(); i++) {
- if (resources[i].enabled) {
- int j;
- COMPUTE_DBG(ctx->screen, "resnum: %i, cdw: %i\n", i, cs->cdw);
-
- for (j = 0; j < resources[i].cs_end; j++) {
- if (resources[i].do_reloc[j]) {
- assert(resources[i].bo);
- evergreen_emit_ctx_reloc(ctx,
- resources[i].bo,
- resources[i].usage);
- }
-
- cs->buf[cs->cdw++] = resources[i].cs[j];
- }
-
- if (resources[i].bo) {
- evergreen_emit_ctx_reloc(ctx,
- resources[i].bo,
- resources[i].usage);
-
- ///special case for textures
- if (resources[i].do_reloc
- [resources[i].cs_end] == 2) {
- evergreen_emit_ctx_reloc(ctx,
- resources[i].bo,
- resources[i].usage);
- }
- }
- }
- }
-
/* Emit dispatch state and dispatch packet */
evergreen_emit_direct_dispatch(ctx, block_layout, grid_layout);
/* XXX evergreen_flush_emit() hardcodes the CP_COHER_SIZE to 0xffffffff
*/
- ctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
+ ctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
+ R600_CONTEXT_INV_VERTEX_CACHE |
+ R600_CONTEXT_INV_TEX_CACHE;
r600_flush_emit(ctx);
+ ctx->b.flags = 0;
#if 0
COMPUTE_DBG(ctx->screen, "cdw: %i\n", cs->cdw);
for (i = 0; i < cs->cdw; i++) {
- COMPUTE_DBG(ctx->screen, "%4i : 0x%08X\n", i, ctx->cs->buf[i]);
+ COMPUTE_DBG(ctx->screen, "%4i : 0x%08X\n", i, cs->buf[i]);
}
#endif
- flush_flags = RADEON_FLUSH_ASYNC | RADEON_FLUSH_COMPUTE;
- if (ctx->keep_tiling_flags) {
- flush_flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
- }
-
- ctx->ws->cs_flush(ctx->rings.gfx.cs, flush_flags);
-
- ctx->flags = 0;
-
- COMPUTE_DBG(ctx->screen, "shader started\n");
}
(struct r600_cs_shader_state*)atom;
struct r600_pipe_compute *shader = state->shader;
struct r600_kernel *kernel = &shader->kernels[state->kernel_index];
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
uint64_t va;
- va = r600_resource_va(&rctx->screen->screen, &kernel->code_bo->b.b);
+ va = r600_resource_va(&rctx->screen->b.b, &kernel->code_bo->b.b);
r600_write_compute_context_reg_seq(cs, R_0288D0_SQ_PGM_START_LS, 3);
- r600_write_value(cs, va >> 8); /* R_0288D0_SQ_PGM_START_LS */
- r600_write_value(cs, /* R_0288D4_SQ_PGM_RESOURCES_LS */
+ radeon_emit(cs, va >> 8); /* R_0288D0_SQ_PGM_START_LS */
+ radeon_emit(cs, /* R_0288D4_SQ_PGM_RESOURCES_LS */
S_0288D4_NUM_GPRS(kernel->bc.ngpr)
| S_0288D4_STACK_SIZE(kernel->bc.nstack));
- r600_write_value(cs, 0); /* R_0288D8_SQ_PGM_RESOURCES_LS_2 */
+ radeon_emit(cs, 0); /* R_0288D8_SQ_PGM_RESOURCES_LS_2 */
- r600_write_value(cs, PKT3C(PKT3_NOP, 0, 0));
- r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx,
+ radeon_emit(cs, PKT3C(PKT3_NOP, 0, 0));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
kernel->code_bo, RADEON_USAGE_READ));
-
- rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
}
static void evergreen_launch_grid(
{
struct r600_context *ctx = (struct r600_context *)ctx_;
-#ifdef HAVE_OPENCL
+ struct r600_pipe_compute *shader = ctx->cs_shader_state.shader;
+ struct r600_kernel *kernel = &shader->kernels[pc];
+
COMPUTE_DBG(ctx->screen, "*** evergreen_launch_grid: pc = %u\n", pc);
- struct r600_pipe_compute *shader = ctx->cs_shader_state.shader;
- if (!shader->kernels[pc].code_bo) {
+#ifdef HAVE_OPENCL
+
+ if (!kernel->code_bo) {
void *p;
- struct r600_kernel *kernel = &shader->kernels[pc];
- r600_compute_shader_create(ctx_, kernel->llvm_module, &kernel->bc);
+ struct r600_bytecode *bc = &kernel->bc;
+ LLVMModuleRef mod = kernel->llvm_module;
+ boolean use_kill = false;
+ bool dump = (ctx->screen->b.debug_flags & DBG_CS) != 0;
+ unsigned use_sb = ctx->screen->b.debug_flags & DBG_SB_CS;
+ unsigned sb_disasm = use_sb ||
+ (ctx->screen->b.debug_flags & DBG_SB_DISASM);
+
+ r600_bytecode_init(bc, ctx->b.chip_class, ctx->b.family,
+ ctx->screen->has_compressed_msaa_texturing);
+ bc->type = TGSI_PROCESSOR_COMPUTE;
+ bc->isa = ctx->isa;
+ r600_llvm_compile(mod, ctx->b.family, bc, &use_kill, dump);
+
+ if (dump && !sb_disasm) {
+ r600_bytecode_disasm(bc);
+ } else if ((dump && sb_disasm) || use_sb) {
+ if (r600_sb_bytecode_process(ctx, bc, NULL, dump, use_sb))
+ R600_ERR("r600_sb_bytecode_process failed!\n");
+ }
+
kernel->code_bo = r600_compute_buffer_alloc_vram(ctx->screen,
kernel->bc.ndw * 4);
- p = r600_buffer_mmap_sync_with_rings(ctx, kernel->code_bo, PIPE_TRANSFER_WRITE);
+ p = r600_buffer_map_sync_with_rings(&ctx->b, kernel->code_bo, PIPE_TRANSFER_WRITE);
memcpy(p, kernel->bc.bytecode, kernel->bc.ndw * 4);
- ctx->ws->buffer_unmap(kernel->code_bo->cs_buf);
+ ctx->b.ws->buffer_unmap(kernel->code_bo->cs_buf);
}
#endif
-
+ shader->active_kernel = kernel;
ctx->cs_shader_state.kernel_index = pc;
evergreen_compute_upload_input(ctx_, block_layout, grid_layout, input);
compute_emit_cs(ctx, block_layout, grid_layout);
unsigned start_slot, unsigned count,
struct pipe_sampler_view **views)
{
- struct r600_context *ctx = (struct r600_context *)ctx_;
struct r600_pipe_sampler_view **resource =
(struct r600_pipe_sampler_view **)views;
for (int i = 0; i < count; i++) {
if (resource[i]) {
assert(i+1 < 12);
+ /* XXX: Implement */
+ assert(!"Compute samplers not implemented.");
///FETCH0 = VTX0 (param buffer),
//FETCH1 = VTX1 (global buffer pool), FETCH2... = TEX
- evergreen_set_tex_resource(ctx->cs_shader_state.shader, resource[i], i+2);
}
}
}
-static void evergreen_bind_compute_sampler_states(
- struct pipe_context *ctx_,
- unsigned start_slot,
- unsigned num_samplers,
- void **samplers_)
-{
- struct r600_context *ctx = (struct r600_context *)ctx_;
- struct compute_sampler_state ** samplers =
- (struct compute_sampler_state **)samplers_;
-
- for (int i = 0; i < num_samplers; i++) {
- if (samplers[i]) {
- evergreen_set_sampler_resource(
- ctx->cs_shader_state.shader, samplers[i], i);
- }
- }
-}
static void evergreen_set_global_binding(
struct pipe_context *ctx_, unsigned first, unsigned n,
r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
- switch (ctx->family) {
+ switch (ctx->b.family) {
case CHIP_CEDAR:
default:
num_threads = 128;
}
/* Config Registers */
- if (ctx->chip_class < CAYMAN)
- evergreen_init_common_regs(cb, ctx->chip_class, ctx->family,
- ctx->screen->info.drm_minor);
+ if (ctx->b.chip_class < CAYMAN)
+ evergreen_init_common_regs(cb, ctx->b.chip_class, ctx->b.family,
+ ctx->screen->b.info.drm_minor);
else
- cayman_init_common_regs(cb, ctx->chip_class, ctx->family,
- ctx->screen->info.drm_minor);
+ cayman_init_common_regs(cb, ctx->b.chip_class, ctx->b.family,
+ ctx->screen->b.info.drm_minor);
/* The primitive type always needs to be POINTLIST for compute. */
r600_store_config_reg(cb, R_008958_VGT_PRIMITIVE_TYPE,
V_008958_DI_PT_POINTLIST);
- if (ctx->chip_class < CAYMAN) {
+ if (ctx->b.chip_class < CAYMAN) {
/* These registers control which simds can be used by each stage.
* The default for these registers is 0xffffffff, which means
r600_store_value(cb,
S_008C28_NUM_LS_STACK_ENTRIES(num_stack_entries));
}
+ /* Give the compute shader all the available LDS space.
+ * NOTE: This only sets the maximum number of dwords that a compute
+ * shader can allocate. When a shader is executed, we still need to
+ * allocate the appropriate amount of LDS dwords using the
+ * CM_R_0288E8_SQ_LDS_ALLOC register.
+ */
+ if (ctx->b.chip_class < CAYMAN) {
+ r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
+ S_008E2C_NUM_PS_LDS(0x0000) | S_008E2C_NUM_LS_LDS(8192));
+ } else {
+ r600_store_context_reg(cb, CM_R_0286FC_SPI_LDS_MGMT,
+ S_0286FC_NUM_PS_LDS(0) |
+ S_0286FC_NUM_LS_LDS(255)); /* 255 * 32 = 8160 dwords */
+ }
/* Context Registers */
- if (ctx->chip_class < CAYMAN) {
+ if (ctx->b.chip_class < CAYMAN) {
/* workaround for hw issues with dyn gpr - must set all limits
* to 240 instead of 0, 0x1e == 240 / 8
*/
void evergreen_init_compute_state_functions(struct r600_context *ctx)
{
- ctx->context.create_compute_state = evergreen_create_compute_state;
- ctx->context.delete_compute_state = evergreen_delete_compute_state;
- ctx->context.bind_compute_state = evergreen_bind_compute_state;
+ ctx->b.b.create_compute_state = evergreen_create_compute_state;
+ ctx->b.b.delete_compute_state = evergreen_delete_compute_state;
+ ctx->b.b.bind_compute_state = evergreen_bind_compute_state;
// ctx->context.create_sampler_view = evergreen_compute_create_sampler_view;
- ctx->context.set_compute_resources = evergreen_set_compute_resources;
- ctx->context.set_compute_sampler_views = evergreen_set_cs_sampler_view;
- ctx->context.bind_compute_sampler_states = evergreen_bind_compute_sampler_states;
- ctx->context.set_global_binding = evergreen_set_global_binding;
- ctx->context.launch_grid = evergreen_launch_grid;
+ ctx->b.b.set_compute_resources = evergreen_set_compute_resources;
+ ctx->b.b.set_compute_sampler_views = evergreen_set_cs_sampler_view;
+ ctx->b.b.set_global_binding = evergreen_set_global_binding;
+ ctx->b.b.launch_grid = evergreen_launch_grid;
/* We always use at least one vertex buffer for parameters (id = 1)*/
ctx->cs_vertex_buffer_state.enabled_mask =
ctx->cs_vertex_buffer_state.dirty_mask = 0x2;
}
-
struct pipe_resource *r600_compute_global_buffer_create(
struct pipe_screen *screen,
const struct pipe_resource *templ)
{
struct r600_context *rctx = (struct r600_context*)ctx_;
struct compute_memory_pool *pool = rctx->screen->global_pool;
- struct pipe_transfer *transfer = util_slab_alloc(&rctx->pool_transfers);
struct r600_resource_global* buffer =
(struct r600_resource_global*)resource;
- uint32_t* map;
-
- compute_memory_finalize_pending(pool, ctx_);
- assert(resource->target == PIPE_BUFFER);
-
- COMPUTE_DBG(rctx->screen, "* r600_compute_global_get_transfer()\n"
+ COMPUTE_DBG(rctx->screen, "* r600_compute_global_transfer_map()\n"
"level = %u, usage = %u, box(x = %u, y = %u, z = %u "
"width = %u, height = %u, depth = %u)\n", level, usage,
box->x, box->y, box->z, box->width, box->height,
box->depth);
+ COMPUTE_DBG(rctx->screen, "Buffer id = %u offset = "
+ "%u (box.x)\n", buffer->chunk->id, box->x);
- transfer->resource = resource;
- transfer->level = level;
- transfer->usage = usage;
- transfer->box = *box;
- transfer->stride = 0;
- transfer->layer_stride = 0;
-
- assert(transfer->resource->target == PIPE_BUFFER);
- assert(transfer->resource->bind & PIPE_BIND_GLOBAL);
- assert(transfer->box.x >= 0);
- assert(transfer->box.y == 0);
- assert(transfer->box.z == 0);
-
- ///TODO: do it better, mapping is not possible if the pool is too big
- COMPUTE_DBG(rctx->screen, "* r600_compute_global_transfer_map()\n");
-
- if (!(map = r600_buffer_mmap_sync_with_rings(rctx, buffer->chunk->pool->bo, transfer->usage))) {
- util_slab_free(&rctx->pool_transfers, transfer);
- return NULL;
- }
+ compute_memory_finalize_pending(pool, ctx_);
- *ptransfer = transfer;
+ assert(resource->target == PIPE_BUFFER);
+ assert(resource->bind & PIPE_BIND_GLOBAL);
+ assert(box->x >= 0);
+ assert(box->y == 0);
+ assert(box->z == 0);
- COMPUTE_DBG(rctx->screen, "Buffer: %p + %u (buffer offset in global memory) "
- "+ %u (box.x)\n", map, buffer->chunk->start_in_dw, transfer->box.x);
- return ((char*)(map + buffer->chunk->start_in_dw)) + transfer->box.x;
+ ///TODO: do it better, mapping is not possible if the pool is too big
+ return pipe_buffer_map_range(ctx_, (struct pipe_resource*)buffer->chunk->pool->bo,
+ box->x + (buffer->chunk->start_in_dw * 4),
+ box->width, usage, ptransfer);
}
void r600_compute_global_transfer_unmap(
struct pipe_context *ctx_,
struct pipe_transfer* transfer)
{
- struct r600_context *ctx = NULL;
- struct r600_resource_global* buffer = NULL;
-
- assert(transfer->resource->target == PIPE_BUFFER);
- assert(transfer->resource->bind & PIPE_BIND_GLOBAL);
-
- ctx = (struct r600_context *)ctx_;
- buffer = (struct r600_resource_global*)transfer->resource;
-
- COMPUTE_DBG(ctx->screen, "* r600_compute_global_transfer_unmap()\n");
-
- ctx->ws->buffer_unmap(buffer->chunk->pool->bo->cs_buf);
- util_slab_free(&ctx->pool_transfers, transfer);
+ /* struct r600_resource_global are not real resources, they just map
+ * to an offset within the compute memory pool. The function
+ * r600_compute_global_transfer_map() maps the memory pool
+ * resource rather than the struct r600_resource_global passed to
+ * it as an argument and then initalizes ptransfer->resource with
+ * the memory pool resource (via pipe_buffer_map_range).
+ * When transfer_unmap is called it uses the memory pool's
+ * vtable which calls r600_buffer_transfer_map() rather than
+ * this function.
+ */
+ assert (!"This function should not be called");
}
void r600_compute_global_transfer_flush_region(
projects / mesa.git / blobdiff