#include "util/u_inlines.h"
#include "util/u_framebuffer.h"
#include "pipebuffer/pb_buffer.h"
-#include "r600.h"
#include "evergreend.h"
#include "r600_resource.h"
#include "r600_shader.h"
#include "r600_pipe.h"
#include "r600_formats.h"
#include "evergreen_compute.h"
-#include "r600_hw_context_priv.h"
#include "evergreen_compute_internal.h"
#include "compute_memory_pool.h"
#ifdef HAVE_OPENCL
-#include "llvm_wrapper.h"
+#include "radeon_llvm_util.h"
#endif
/**
*/
+struct r600_resource* r600_compute_buffer_alloc_vram(
+ struct r600_screen *screen,
+ unsigned size)
+{
+ struct pipe_resource * buffer = NULL;
+ assert(size);
+
+ buffer = pipe_buffer_create(
+ (struct pipe_screen*) screen,
+ PIPE_BIND_CUSTOM,
+ PIPE_USAGE_IMMUTABLE,
+ size);
+
+ return (struct r600_resource *)buffer;
+}
+
+
+static void evergreen_set_rat(
+ struct r600_pipe_compute *pipe,
+ int id,
+ struct r600_resource* bo,
+ int start,
+ int size)
+{
+ struct pipe_surface rat_templ;
+ struct r600_surface *surf = NULL;
+ struct r600_context *rctx = NULL;
+
+ assert(id < 12);
+ assert((size & 3) == 0);
+ assert((start & 0xFF) == 0);
+
+ rctx = pipe->ctx;
+
+ COMPUTE_DBG(rctx->screen, "bind rat: %i \n", id);
+
+ /* Create the RAT surface */
+ memset(&rat_templ, 0, sizeof(rat_templ));
+ rat_templ.format = PIPE_FORMAT_R32_UINT;
+ rat_templ.u.tex.level = 0;
+ rat_templ.u.tex.first_layer = 0;
+ rat_templ.u.tex.last_layer = 0;
+
+ /* Add the RAT the list of color buffers */
+ pipe->ctx->framebuffer.state.cbufs[id] = pipe->ctx->context.create_surface(
+ (struct pipe_context *)pipe->ctx,
+ (struct pipe_resource *)bo, &rat_templ);
+
+ /* Update the number of color buffers */
+ pipe->ctx->framebuffer.state.nr_cbufs =
+ MAX2(id + 1, pipe->ctx->framebuffer.state.nr_cbufs);
+
+ /* Update the cb_target_mask
+ * XXX: I think this is a potential spot for bugs once we start doing
+ * GL interop. cb_target_mask may be modified in the 3D sections
+ * of this driver. */
+ pipe->ctx->compute_cb_target_mask |= (0xf << (id * 4));
+
+ surf = (struct r600_surface*)pipe->ctx->framebuffer.state.cbufs[id];
+ evergreen_init_color_surface_rat(rctx, surf);
+}
+
static void evergreen_cs_set_vertex_buffer(
struct r600_context * rctx,
unsigned vb_index,
vb->buffer = buffer;
vb->user_buffer = NULL;
- r600_inval_vertex_cache(rctx);
+ /* The vertex instructions in the compute shaders use the texture cache,
+ * so we need to invalidate it. */
+ rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
state->enabled_mask |= 1 << vb_index;
state->dirty_mask |= 1 << vb_index;
- r600_atom_dirty(rctx, &state->atom);
+ state->atom.dirty = true;
}
-const struct u_resource_vtbl r600_global_buffer_vtbl =
+static void evergreen_cs_set_constant_buffer(
+ struct r600_context * rctx,
+ unsigned cb_index,
+ unsigned offset,
+ unsigned size,
+ struct pipe_resource * buffer)
+{
+ struct pipe_constant_buffer cb;
+ cb.buffer_size = size;
+ cb.buffer_offset = offset;
+ cb.buffer = buffer;
+ cb.user_buffer = NULL;
+
+ rctx->context.set_constant_buffer(&rctx->context, PIPE_SHADER_COMPUTE, cb_index, &cb);
+}
+
+static const struct u_resource_vtbl r600_global_buffer_vtbl =
{
u_default_resource_get_handle, /* get_handle */
r600_compute_global_buffer_destroy, /* resource_destroy */
- r600_compute_global_get_transfer, /* get_transfer */
- r600_compute_global_transfer_destroy, /* transfer_destroy */
r600_compute_global_transfer_map, /* transfer_map */
r600_compute_global_transfer_flush_region,/* transfer_flush_region */
r600_compute_global_transfer_unmap, /* transfer_unmap */
{
struct r600_context *ctx = (struct r600_context *)ctx_;
struct r600_pipe_compute *shader = CALLOC_STRUCT(r600_pipe_compute);
- void *p;
#ifdef HAVE_OPENCL
const struct pipe_llvm_program_header * header;
const unsigned char * code;
+ unsigned i;
- COMPUTE_DBG("*** evergreen_create_compute_state\n");
+ COMPUTE_DBG(ctx->screen, "*** evergreen_create_compute_state\n");
header = cso->prog;
code = cso->prog + sizeof(struct pipe_llvm_program_header);
#endif
shader->ctx = (struct r600_context*)ctx;
- shader->resources = (struct evergreen_compute_resource*)
- CALLOC(sizeof(struct evergreen_compute_resource),
- get_compute_resource_num());
shader->local_size = cso->req_local_mem; ///TODO: assert it
shader->private_size = cso->req_private_mem;
shader->input_size = cso->req_input_mem;
#ifdef HAVE_OPENCL
- shader->mod = llvm_parse_bitcode(code, header->num_bytes);
+ shader->num_kernels = radeon_llvm_get_num_kernels(code, header->num_bytes);
+ shader->kernels = CALLOC(sizeof(struct r600_kernel), shader->num_kernels);
- r600_compute_shader_create(ctx_, shader->mod, &shader->bc);
+ for (i = 0; i < shader->num_kernels; i++) {
+ struct r600_kernel *kernel = &shader->kernels[i];
+ kernel->llvm_module = radeon_llvm_get_kernel_module(i, code,
+ header->num_bytes);
+ }
#endif
- shader->shader_code_bo = r600_compute_buffer_alloc_vram(ctx->screen,
- shader->bc.ndw * 4);
-
- p = ctx->ws->buffer_map(shader->shader_code_bo->cs_buf, ctx->cs,
- PIPE_TRANSFER_WRITE);
-
- memcpy(p, shader->bc.bytecode, shader->bc.ndw * 4);
- ctx->ws->buffer_unmap(shader->shader_code_bo->cs_buf);
return shader;
}
{
struct r600_pipe_compute *shader = (struct r600_pipe_compute *)state;
- free(shader->resources);
free(shader);
}
{
struct r600_context *ctx = (struct r600_context *)ctx_;
- COMPUTE_DBG("*** evergreen_bind_compute_state\n");
+ COMPUTE_DBG(ctx->screen, "*** evergreen_bind_compute_state\n");
ctx->cs_shader_state.shader = (struct r600_pipe_compute *)state;
}
struct r600_context *ctx = (struct r600_context *)ctx_;
struct r600_pipe_compute *shader = ctx->cs_shader_state.shader;
int i;
- unsigned kernel_parameters_offset_bytes = 36;
+ /* We need to reserve 9 dwords (36 bytes) for implicit kernel
+ * parameters.
+ */
+ unsigned input_size = shader->input_size + 36;
uint32_t * num_work_groups_start;
uint32_t * global_size_start;
uint32_t * local_size_start;
uint32_t * kernel_parameters_start;
+ struct pipe_box box;
+ struct pipe_transfer *transfer = NULL;
if (shader->input_size == 0) {
return;
}
if (!shader->kernel_param) {
- unsigned buffer_size = shader->input_size;
-
/* Add space for the grid dimensions */
- buffer_size += kernel_parameters_offset_bytes * sizeof(uint);
- shader->kernel_param = r600_compute_buffer_alloc_vram(
- ctx->screen, buffer_size);
+ shader->kernel_param = (struct r600_resource *)
+ pipe_buffer_create(ctx_->screen, PIPE_BIND_CUSTOM,
+ PIPE_USAGE_IMMUTABLE, input_size);
}
- num_work_groups_start = ctx->ws->buffer_map(
- shader->kernel_param->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE);
+ u_box_1d(0, input_size, &box);
+ num_work_groups_start = ctx_->transfer_map(ctx_,
+ (struct pipe_resource*)shader->kernel_param,
+ 0, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_DISCARD_RANGE,
+ &box, &transfer);
global_size_start = num_work_groups_start + (3 * (sizeof(uint) /4));
local_size_start = global_size_start + (3 * (sizeof(uint)) / 4);
kernel_parameters_start = local_size_start + (3 * (sizeof(uint)) / 4);
/* Copy the kernel inputs */
memcpy(kernel_parameters_start, input, shader->input_size);
- for (i = 0; i < (kernel_parameters_offset_bytes / 4) +
- (shader->input_size / 4); i++) {
- COMPUTE_DBG("input %i : %i\n", i,
+ for (i = 0; i < (input_size / 4); i++) {
+ COMPUTE_DBG(ctx->screen, "input %i : %i\n", i,
((unsigned*)num_work_groups_start)[i]);
}
- ctx->ws->buffer_unmap(shader->kernel_param->cs_buf);
+ ctx_->transfer_unmap(ctx_, transfer);
- ///ID=0 is reserved for the parameters
- evergreen_cs_set_vertex_buffer(ctx, 0, 0,
+ /* ID=0 is reserved for the parameters */
+ evergreen_cs_set_constant_buffer(ctx, 0, 0, input_size,
(struct pipe_resource*)shader->kernel_param);
- ///ID=0 is reserved for parameters
- evergreen_set_const_cache(shader, 0, shader->kernel_param,
- shader->input_size, 0);
}
static void evergreen_emit_direct_dispatch(
const uint *block_layout, const uint *grid_layout)
{
int i;
- struct radeon_winsys_cs *cs = rctx->cs;
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
unsigned num_waves;
unsigned num_pipes = rctx->screen->info.r600_max_pipes;
unsigned wave_divisor = (16 * num_pipes);
num_waves = (block_layout[0] * block_layout[1] * block_layout[2] +
wave_divisor - 1) / wave_divisor;
- COMPUTE_DBG("Using %u pipes, there are %u wavefronts per thread block\n",
+ COMPUTE_DBG(rctx->screen, "Using %u pipes, there are %u wavefronts per thread block\n",
num_pipes, num_waves);
/* XXX: Partition the LDS between PS/CS. By default half (4096 dwords
static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout,
const uint *grid_layout)
{
- struct radeon_winsys_cs *cs = ctx->cs;
+ struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
+ unsigned flush_flags = 0;
int i;
- struct r600_resource *onebo = NULL;
- struct r600_pipe_state *cb_state;
- struct evergreen_compute_resource *resources =
- ctx->cs_shader_state.shader->resources;
+ /* make sure that the gfx ring is only one active */
+ if (ctx->rings.dma.cs) {
+ ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+ }
/* Initialize all the compute-related registers.
*
* See evergreen_init_atom_start_compute_cs() in this file for the list
* of registers initialized by the start_compute_cs_cmd atom.
*/
- r600_emit_atom(ctx, &ctx->start_compute_cs_cmd.atom);
+ r600_emit_command_buffer(cs, &ctx->start_compute_cs_cmd);
+
+ ctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
+ r600_flush_emit(ctx);
+
+ /* Emit colorbuffers. */
+ for (i = 0; i < ctx->framebuffer.state.nr_cbufs; i++) {
+ struct r600_surface *cb = (struct r600_surface*)ctx->framebuffer.state.cbufs[i];
+ unsigned reloc = r600_context_bo_reloc(ctx, &ctx->rings.gfx,
+ (struct r600_resource*)cb->base.texture,
+ RADEON_USAGE_READWRITE);
+
+ r600_write_compute_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 7);
+ r600_write_value(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
+ r600_write_value(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
+ r600_write_value(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
+ r600_write_value(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
+ r600_write_value(cs, cb->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
+ r600_write_value(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
+ r600_write_value(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
+
+ r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
+ r600_write_value(cs, reloc);
+
+ if (!ctx->keep_tiling_flags) {
+ r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
+ r600_write_value(cs, reloc);
+ }
- /* Emit cb_state */
- cb_state = ctx->states[R600_PIPE_STATE_FRAMEBUFFER];
- r600_context_pipe_state_emit(ctx, cb_state, RADEON_CP_PACKET3_COMPUTE_MODE);
+ r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
+ r600_write_value(cs, reloc);
+ }
/* Set CB_TARGET_MASK XXX: Use cb_misc_state */
r600_write_compute_context_reg(cs, R_028238_CB_TARGET_MASK,
ctx->cs_vertex_buffer_state.atom.num_dw = 12 * util_bitcount(ctx->cs_vertex_buffer_state.dirty_mask);
r600_emit_atom(ctx, &ctx->cs_vertex_buffer_state.atom);
+ /* Emit constant buffer state */
+ r600_emit_atom(ctx, &ctx->constbuf_state[PIPE_SHADER_COMPUTE].atom);
+
/* Emit compute shader state */
r600_emit_atom(ctx, &ctx->cs_shader_state.atom);
- for (i = 0; i < get_compute_resource_num(); i++) {
- if (resources[i].enabled) {
- int j;
- COMPUTE_DBG("resnum: %i, cdw: %i\n", i, cs->cdw);
-
- for (j = 0; j < resources[i].cs_end; j++) {
- if (resources[i].do_reloc[j]) {
- assert(resources[i].bo);
- evergreen_emit_ctx_reloc(ctx,
- resources[i].bo,
- resources[i].usage);
- }
-
- cs->buf[cs->cdw++] = resources[i].cs[j];
- }
-
- if (resources[i].bo) {
- onebo = resources[i].bo;
- evergreen_emit_ctx_reloc(ctx,
- resources[i].bo,
- resources[i].usage);
-
- ///special case for textures
- if (resources[i].do_reloc
- [resources[i].cs_end] == 2) {
- evergreen_emit_ctx_reloc(ctx,
- resources[i].bo,
- resources[i].usage);
- }
- }
- }
- }
-
/* Emit dispatch state and dispatch packet */
evergreen_emit_direct_dispatch(ctx, block_layout, grid_layout);
- /* r600_flush_framebuffer() updates the cb_flush_flags and then
- * calls r600_emit_atom() on the ctx->surface_sync_cmd.atom, which emits
- * a SURFACE_SYNC packet via r600_emit_surface_sync().
- *
- * XXX r600_emit_surface_sync() hardcodes the CP_COHER_SIZE to
- * 0xffffffff, so we will need to add a field to struct
- * r600_surface_sync_cmd if we want to manually set this value.
+ /* XXX evergreen_flush_emit() hardcodes the CP_COHER_SIZE to 0xffffffff
*/
- r600_flush_framebuffer(ctx, true /* Flush now */);
+ ctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
+ r600_flush_emit(ctx);
#if 0
- COMPUTE_DBG("cdw: %i\n", cs->cdw);
+ COMPUTE_DBG(ctx->screen, "cdw: %i\n", cs->cdw);
for (i = 0; i < cs->cdw; i++) {
- COMPUTE_DBG("%4i : 0x%08X\n", i, ctx->cs->buf[i]);
+ COMPUTE_DBG(ctx->screen, "%4i : 0x%08X\n", i, cs->buf[i]);
}
#endif
- ctx->ws->cs_flush(ctx->cs, RADEON_FLUSH_ASYNC | RADEON_FLUSH_COMPUTE);
-
- ctx->pm4_dirty_cdwords = 0;
- ctx->flags = 0;
-
- COMPUTE_DBG("shader started\n");
-
- ctx->ws->buffer_wait(onebo->buf, 0);
+ flush_flags = RADEON_FLUSH_ASYNC | RADEON_FLUSH_COMPUTE;
+ if (ctx->keep_tiling_flags) {
+ flush_flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
+ }
- COMPUTE_DBG("...\n");
+ ctx->ws->cs_flush(ctx->rings.gfx.cs, flush_flags, ctx->screen->cs_count++);
- ctx->streamout_start = TRUE;
- ctx->streamout_append_bitmask = ~0;
+ ctx->flags = 0;
+ COMPUTE_DBG(ctx->screen, "shader started\n");
}
struct r600_cs_shader_state *state =
(struct r600_cs_shader_state*)atom;
struct r600_pipe_compute *shader = state->shader;
- struct radeon_winsys_cs *cs = rctx->cs;
+ struct r600_kernel *kernel = &shader->kernels[state->kernel_index];
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
uint64_t va;
- va = r600_resource_va(&rctx->screen->screen, &shader->shader_code_bo->b.b);
+ va = r600_resource_va(&rctx->screen->screen, &kernel->code_bo->b.b);
r600_write_compute_context_reg_seq(cs, R_0288D0_SQ_PGM_START_LS, 3);
r600_write_value(cs, va >> 8); /* R_0288D0_SQ_PGM_START_LS */
r600_write_value(cs, /* R_0288D4_SQ_PGM_RESOURCES_LS */
- S_0288D4_NUM_GPRS(shader->bc.ngpr)
- | S_0288D4_STACK_SIZE(shader->bc.nstack));
+ S_0288D4_NUM_GPRS(kernel->bc.ngpr)
+ | S_0288D4_STACK_SIZE(kernel->bc.nstack));
r600_write_value(cs, 0); /* R_0288D8_SQ_PGM_RESOURCES_LS_2 */
r600_write_value(cs, PKT3C(PKT3_NOP, 0, 0));
- r600_write_value(cs, r600_context_bo_reloc(rctx, shader->shader_code_bo,
- RADEON_USAGE_READ));
+ r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx,
+ kernel->code_bo, RADEON_USAGE_READ));
- r600_inval_shader_cache(rctx);
+ rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
}
static void evergreen_launch_grid(
{
struct r600_context *ctx = (struct r600_context *)ctx_;
- COMPUTE_DBG("PC: %i\n", pc);
+#ifdef HAVE_OPENCL
+ COMPUTE_DBG(ctx->screen, "*** evergreen_launch_grid: pc = %u\n", pc);
+
+ struct r600_pipe_compute *shader = ctx->cs_shader_state.shader;
+ if (!shader->kernels[pc].code_bo) {
+ void *p;
+ struct r600_kernel *kernel = &shader->kernels[pc];
+ r600_compute_shader_create(ctx_, kernel->llvm_module, &kernel->bc);
+ kernel->code_bo = r600_compute_buffer_alloc_vram(ctx->screen,
+ kernel->bc.ndw * 4);
+ p = r600_buffer_mmap_sync_with_rings(ctx, kernel->code_bo, PIPE_TRANSFER_WRITE);
+ memcpy(p, kernel->bc.bytecode, kernel->bc.ndw * 4);
+ ctx->ws->buffer_unmap(kernel->code_bo->cs_buf);
+ }
+#endif
+ ctx->cs_shader_state.kernel_index = pc;
evergreen_compute_upload_input(ctx_, block_layout, grid_layout, input);
compute_emit_cs(ctx, block_layout, grid_layout);
}
struct r600_context *ctx = (struct r600_context *)ctx_;
struct r600_surface **resources = (struct r600_surface **)surfaces;
- COMPUTE_DBG("*** evergreen_set_compute_resources: start = %u count = %u\n",
+ COMPUTE_DBG(ctx->screen, "*** evergreen_set_compute_resources: start = %u count = %u\n",
start, count);
for (int i = 0; i < count; i++) {
unsigned start_slot, unsigned count,
struct pipe_sampler_view **views)
{
- struct r600_context *ctx = (struct r600_context *)ctx_;
struct r600_pipe_sampler_view **resource =
(struct r600_pipe_sampler_view **)views;
for (int i = 0; i < count; i++) {
if (resource[i]) {
assert(i+1 < 12);
+ /* XXX: Implement */
+ assert(!"Compute samplers not implemented.");
///FETCH0 = VTX0 (param buffer),
//FETCH1 = VTX1 (global buffer pool), FETCH2... = TEX
- evergreen_set_tex_resource(ctx->cs_shader_state.shader, resource[i], i+2);
}
}
}
unsigned num_samplers,
void **samplers_)
{
- struct r600_context *ctx = (struct r600_context *)ctx_;
struct compute_sampler_state ** samplers =
(struct compute_sampler_state **)samplers_;
for (int i = 0; i < num_samplers; i++) {
if (samplers[i]) {
- evergreen_set_sampler_resource(
- ctx->cs_shader_state.shader, samplers[i], i);
+ /* XXX: Implement */
+ assert(!"Compute samplers not implemented.");
}
}
}
struct r600_resource_global **buffers =
(struct r600_resource_global **)resources;
- COMPUTE_DBG("*** evergreen_set_global_binding first = %u n = %u\n",
+ COMPUTE_DBG(ctx->screen, "*** evergreen_set_global_binding first = %u n = %u\n",
first, n);
if (!resources) {
/* since all required registers are initialised in the
* start_compute_cs_cmd atom, we can EMIT_EARLY here.
*/
- r600_init_command_buffer(ctx, cb, 1, 256);
+ r600_init_command_buffer(cb, 256);
cb->pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
+ /* This must be first. */
+ r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
+ r600_store_value(cb, 0x80000000);
+ r600_store_value(cb, 0x80000000);
+
+ /* We're setting config registers here. */
+ r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
+
switch (ctx->family) {
case CHIP_CEDAR:
default:
}
/* Config Registers */
- evergreen_init_common_regs(cb, ctx->chip_class
- , ctx->family, ctx->screen->info.drm_minor);
+ if (ctx->chip_class < CAYMAN)
+ evergreen_init_common_regs(cb, ctx->chip_class, ctx->family,
+ ctx->screen->info.drm_minor);
+ else
+ cayman_init_common_regs(cb, ctx->chip_class, ctx->family,
+ ctx->screen->info.drm_minor);
/* The primitive type always needs to be POINTLIST for compute. */
r600_store_config_reg(cb, R_008958_VGT_PRIMITIVE_TYPE,
ctx->context.set_global_binding = evergreen_set_global_binding;
ctx->context.launch_grid = evergreen_launch_grid;
- /* We always use at least two vertex buffers for compute, one for
- * parameters and one for global memory */
+ /* We always use at least one vertex buffer for parameters (id = 1)*/
ctx->cs_vertex_buffer_state.enabled_mask =
- ctx->cs_vertex_buffer_state.dirty_mask = 1 | 2;
+ ctx->cs_vertex_buffer_state.dirty_mask = 0x2;
}
struct pipe_screen *screen,
const struct pipe_resource *templ)
{
+ struct r600_resource_global* result = NULL;
+ struct r600_screen* rscreen = NULL;
+ int size_in_dw = 0;
+
assert(templ->target == PIPE_BUFFER);
assert(templ->bind & PIPE_BIND_GLOBAL);
assert(templ->array_size == 1 || templ->array_size == 0);
assert(templ->depth0 == 1 || templ->depth0 == 0);
assert(templ->height0 == 1 || templ->height0 == 0);
- struct r600_resource_global* result = (struct r600_resource_global*)
- CALLOC(sizeof(struct r600_resource_global), 1);
- struct r600_screen* rscreen = (struct r600_screen*)screen;
+ result = (struct r600_resource_global*)
+ CALLOC(sizeof(struct r600_resource_global), 1);
+ rscreen = (struct r600_screen*)screen;
- COMPUTE_DBG("*** r600_compute_global_buffer_create\n");
- COMPUTE_DBG("width = %u array_size = %u\n", templ->width0,
+ COMPUTE_DBG(rscreen, "*** r600_compute_global_buffer_create\n");
+ COMPUTE_DBG(rscreen, "width = %u array_size = %u\n", templ->width0,
templ->array_size);
result->base.b.vtbl = &r600_global_buffer_vtbl;
result->base.b.b = *templ;
pipe_reference_init(&result->base.b.b.reference, 1);
- int size_in_dw = (templ->width0+3) / 4;
+ size_in_dw = (templ->width0+3) / 4;
result->chunk = compute_memory_alloc(rscreen->global_pool, size_in_dw);
struct pipe_screen *screen,
struct pipe_resource *res)
{
+ struct r600_resource_global* buffer = NULL;
+ struct r600_screen* rscreen = NULL;
+
assert(res->target == PIPE_BUFFER);
assert(res->bind & PIPE_BIND_GLOBAL);
- struct r600_resource_global* buffer = (struct r600_resource_global*)res;
- struct r600_screen* rscreen = (struct r600_screen*)screen;
+ buffer = (struct r600_resource_global*)res;
+ rscreen = (struct r600_screen*)screen;
compute_memory_free(rscreen->global_pool, buffer->chunk->id);
free(res);
}
-void* r600_compute_global_transfer_map(
- struct pipe_context *ctx_,
- struct pipe_transfer* transfer)
-{
- assert(transfer->resource->target == PIPE_BUFFER);
- assert(transfer->resource->bind & PIPE_BIND_GLOBAL);
- assert(transfer->box.x >= 0);
- assert(transfer->box.y == 0);
- assert(transfer->box.z == 0);
-
- struct r600_context *ctx = (struct r600_context *)ctx_;
- struct r600_resource_global* buffer =
- (struct r600_resource_global*)transfer->resource;
-
- uint32_t* map;
- ///TODO: do it better, mapping is not possible if the pool is too big
-
- if (!(map = ctx->ws->buffer_map(buffer->chunk->pool->bo->cs_buf,
- ctx->cs, transfer->usage))) {
- return NULL;
- }
-
- COMPUTE_DBG("buffer start: %lli\n", buffer->chunk->start_in_dw);
- return ((char*)(map + buffer->chunk->start_in_dw)) + transfer->box.x;
-}
-
-void r600_compute_global_transfer_unmap(
- struct pipe_context *ctx_,
- struct pipe_transfer* transfer)
-{
- assert(transfer->resource->target == PIPE_BUFFER);
- assert(transfer->resource->bind & PIPE_BIND_GLOBAL);
-
- struct r600_context *ctx = (struct r600_context *)ctx_;
- struct r600_resource_global* buffer =
- (struct r600_resource_global*)transfer->resource;
-
- ctx->ws->buffer_unmap(buffer->chunk->pool->bo->cs_buf);
-}
-
-struct pipe_transfer * r600_compute_global_get_transfer(
+void *r600_compute_global_transfer_map(
struct pipe_context *ctx_,
struct pipe_resource *resource,
unsigned level,
unsigned usage,
- const struct pipe_box *box)
+ const struct pipe_box *box,
+ struct pipe_transfer **ptransfer)
{
- struct r600_context *ctx = (struct r600_context *)ctx_;
- struct compute_memory_pool *pool = ctx->screen->global_pool;
+ struct r600_context *rctx = (struct r600_context*)ctx_;
+ struct compute_memory_pool *pool = rctx->screen->global_pool;
+ struct r600_resource_global* buffer =
+ (struct r600_resource_global*)resource;
+
+ COMPUTE_DBG(rctx->screen, "* r600_compute_global_transfer_map()\n"
+ "level = %u, usage = %u, box(x = %u, y = %u, z = %u "
+ "width = %u, height = %u, depth = %u)\n", level, usage,
+ box->x, box->y, box->z, box->width, box->height,
+ box->depth);
+ COMPUTE_DBG(rctx->screen, "Buffer: %u (buffer offset in global memory) "
+ "+ %u (box.x)\n", buffer->chunk->start_in_dw, box->x);
+
compute_memory_finalize_pending(pool, ctx_);
assert(resource->target == PIPE_BUFFER);
- struct r600_context *rctx = (struct r600_context*)ctx_;
- struct pipe_transfer *transfer = util_slab_alloc(&rctx->pool_transfers);
-
- transfer->resource = resource;
- transfer->level = level;
- transfer->usage = usage;
- transfer->box = *box;
- transfer->stride = 0;
- transfer->layer_stride = 0;
- transfer->data = NULL;
-
- /* Note strides are zero, this is ok for buffers, but not for
- * textures 2d & higher at least.
- */
- return transfer;
+ assert(resource->bind & PIPE_BIND_GLOBAL);
+ assert(box->x >= 0);
+ assert(box->y == 0);
+ assert(box->z == 0);
+
+ ///TODO: do it better, mapping is not possible if the pool is too big
+ return pipe_buffer_map_range(ctx_, (struct pipe_resource*)buffer->chunk->pool->bo,
+ box->x + (buffer->chunk->start_in_dw * 4),
+ box->width, usage, ptransfer);
}
-void r600_compute_global_transfer_destroy(
+void r600_compute_global_transfer_unmap(
struct pipe_context *ctx_,
- struct pipe_transfer *transfer)
+ struct pipe_transfer* transfer)
{
- struct r600_context *rctx = (struct r600_context*)ctx_;
- util_slab_free(&rctx->pool_transfers, transfer);
+ /* struct r600_resource_global are not real resources, they just map
+ * to an offset within the compute memory pool. The function
+ * r600_compute_global_transfer_map() maps the memory pool
+ * resource rather than the struct r600_resource_global passed to
+ * it as an argument and then initalizes ptransfer->resource with
+ * the memory pool resource (via pipe_buffer_map_range).
+ * When transfer_unmap is called it uses the memory pool's
+ * vtable which calls r600_buffer_transfer_map() rather than
+ * this function.
+ */
+ assert (!"This function should not be called");
}
void r600_compute_global_transfer_flush_region(
projects / mesa.git / blobdiff