r600g/compute: always CONTEXT_CONTROL packet at start of CS

[mesa.git] / src / gallium / drivers / r600 / evergreen_compute.c

diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c
index 655cf756186e90896d9796b1a9550d7f8a535d13..ce17d3a61ece49e31134cd7d3bbcd7bee0aefe31 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -626,6 +626,15 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx)
        r600_init_command_buffer(cb, 256);
        cb->pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
 
+       /* This must be first. */
+       r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
+       r600_store_value(cb, 0x80000000);
+       r600_store_value(cb, 0x80000000);
+
+       /* We're setting config registers here. */
+       r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
+       r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
+
        switch (ctx->family) {
        case CHIP_CEDAR:
        default:
@@ -851,7 +860,7 @@ void *r600_compute_global_transfer_map(
        struct compute_memory_pool *pool = rctx->screen->global_pool;
        struct pipe_transfer *transfer = util_slab_alloc(&rctx->pool_transfers);
        struct r600_resource_global* buffer =
-               (struct r600_resource_global*)transfer->resource;
+               (struct r600_resource_global*)resource;
        uint32_t* map;
 
        compute_memory_finalize_pending(pool, ctx_);
@@ -870,7 +879,6 @@ void *r600_compute_global_transfer_map(
        transfer->box = *box;
        transfer->stride = 0;
        transfer->layer_stride = 0;
-       transfer->data = NULL;
 
        assert(transfer->resource->target == PIPE_BUFFER);
        assert(transfer->resource->bind & PIPE_BIND_GLOBAL);