rctx->flags |= R600_CONTEXT_TEX_FLUSH;
state->enabled_mask |= 1 << vb_index;
state->dirty_mask |= 1 << vb_index;
- r600_atom_dirty(rctx, &state->atom);
+ state->atom.dirty = true;
}
-const struct u_resource_vtbl r600_global_buffer_vtbl =
+static const struct u_resource_vtbl r600_global_buffer_vtbl =
{
u_default_resource_get_handle, /* get_handle */
r600_compute_global_buffer_destroy, /* resource_destroy */
- r600_compute_global_get_transfer, /* get_transfer */
- r600_compute_global_transfer_destroy, /* transfer_destroy */
r600_compute_global_transfer_map, /* transfer_map */
r600_compute_global_transfer_flush_region,/* transfer_flush_region */
r600_compute_global_transfer_unmap, /* transfer_unmap */
{
struct r600_context *ctx = (struct r600_context *)ctx_;
struct r600_pipe_compute *shader = CALLOC_STRUCT(r600_pipe_compute);
- void *p;
#ifdef HAVE_OPENCL
const struct pipe_llvm_program_header * header;
const unsigned char * code;
+ unsigned i;
COMPUTE_DBG("*** evergreen_create_compute_state\n");
shader->input_size = cso->req_input_mem;
#ifdef HAVE_OPENCL
- shader->mod = llvm_parse_bitcode(code, header->num_bytes);
+ shader->num_kernels = llvm_get_num_kernels(code, header->num_bytes);
+ shader->kernels = CALLOC(sizeof(struct r600_kernel), shader->num_kernels);
- r600_compute_shader_create(ctx_, shader->mod, &shader->bc);
+ for (i = 0; i < shader->num_kernels; i++) {
+ struct r600_kernel *kernel = &shader->kernels[i];
+ kernel->llvm_module = llvm_get_kernel_module(i, code,
+ header->num_bytes);
+ }
#endif
- shader->shader_code_bo = r600_compute_buffer_alloc_vram(ctx->screen,
- shader->bc.ndw * 4);
-
- p = ctx->ws->buffer_map(shader->shader_code_bo->cs_buf, ctx->cs,
- PIPE_TRANSFER_WRITE);
-
- memcpy(p, shader->bc.bytecode, shader->bc.ndw * 4);
- ctx->ws->buffer_unmap(shader->shader_code_bo->cs_buf);
return shader;
}
const uint *grid_layout)
{
struct radeon_winsys_cs *cs = ctx->cs;
+ unsigned flush_flags = 0;
int i;
struct r600_resource *onebo = NULL;
* See evergreen_init_atom_start_compute_cs() in this file for the list
* of registers initialized by the start_compute_cs_cmd atom.
*/
- r600_emit_atom(ctx, &ctx->start_compute_cs_cmd.atom);
+ r600_emit_command_buffer(ctx->cs, &ctx->start_compute_cs_cmd);
ctx->flags |= R600_CONTEXT_CB_FLUSH;
r600_flush_emit(ctx);
}
#endif
- ctx->ws->cs_flush(ctx->cs, RADEON_FLUSH_ASYNC | RADEON_FLUSH_COMPUTE);
+ flush_flags = RADEON_FLUSH_ASYNC | RADEON_FLUSH_COMPUTE;
+ if (ctx->keep_tiling_flags) {
+ flush_flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
+ }
+
+ ctx->ws->cs_flush(ctx->cs, flush_flags);
ctx->pm4_dirty_cdwords = 0;
ctx->flags = 0;
struct r600_cs_shader_state *state =
(struct r600_cs_shader_state*)atom;
struct r600_pipe_compute *shader = state->shader;
+ struct r600_kernel *kernel = &shader->kernels[state->kernel_index];
struct radeon_winsys_cs *cs = rctx->cs;
uint64_t va;
- va = r600_resource_va(&rctx->screen->screen, &shader->shader_code_bo->b.b);
+ va = r600_resource_va(&rctx->screen->screen, &kernel->code_bo->b.b);
r600_write_compute_context_reg_seq(cs, R_0288D0_SQ_PGM_START_LS, 3);
r600_write_value(cs, va >> 8); /* R_0288D0_SQ_PGM_START_LS */
r600_write_value(cs, /* R_0288D4_SQ_PGM_RESOURCES_LS */
- S_0288D4_NUM_GPRS(shader->bc.ngpr)
- | S_0288D4_STACK_SIZE(shader->bc.nstack));
+ S_0288D4_NUM_GPRS(kernel->bc.ngpr)
+ | S_0288D4_STACK_SIZE(kernel->bc.nstack));
r600_write_value(cs, 0); /* R_0288D8_SQ_PGM_RESOURCES_LS_2 */
r600_write_value(cs, PKT3C(PKT3_NOP, 0, 0));
- r600_write_value(cs, r600_context_bo_reloc(rctx, shader->shader_code_bo,
+ r600_write_value(cs, r600_context_bo_reloc(rctx, kernel->code_bo,
RADEON_USAGE_READ));
rctx->flags |= R600_CONTEXT_SHADERCONST_FLUSH;
{
struct r600_context *ctx = (struct r600_context *)ctx_;
+#ifdef HAVE_OPENCL
COMPUTE_DBG("*** evergreen_launch_grid: pc = %u\n", pc);
+ struct r600_pipe_compute *shader = ctx->cs_shader_state.shader;
+ if (!shader->kernels[pc].code_bo) {
+ void *p;
+ struct r600_kernel *kernel = &shader->kernels[pc];
+ r600_compute_shader_create(ctx_, kernel->llvm_module, &kernel->bc);
+ kernel->code_bo = r600_compute_buffer_alloc_vram(ctx->screen,
+ kernel->bc.ndw * 4);
+ p = ctx->ws->buffer_map(kernel->code_bo->cs_buf, ctx->cs,
+ PIPE_TRANSFER_WRITE);
+ memcpy(p, kernel->bc.bytecode, kernel->bc.ndw * 4);
+ ctx->ws->buffer_unmap(kernel->code_bo->cs_buf);
+ }
+#endif
+
+ ctx->cs_shader_state.kernel_index = pc;
evergreen_compute_upload_input(ctx_, block_layout, grid_layout, input);
compute_emit_cs(ctx, block_layout, grid_layout);
}
/* since all required registers are initialised in the
* start_compute_cs_cmd atom, we can EMIT_EARLY here.
*/
- r600_init_command_buffer(ctx, cb, 1, 256);
+ r600_init_command_buffer(cb, 256);
cb->pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
+ /* This must be first. */
+ r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
+ r600_store_value(cb, 0x80000000);
+ r600_store_value(cb, 0x80000000);
+
+ /* We're setting config registers here. */
+ r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
+
switch (ctx->family) {
case CHIP_CEDAR:
default:
free(res);
}
-void* r600_compute_global_transfer_map(
+void *r600_compute_global_transfer_map(
struct pipe_context *ctx_,
- struct pipe_transfer* transfer)
+ struct pipe_resource *resource,
+ unsigned level,
+ unsigned usage,
+ const struct pipe_box *box,
+ struct pipe_transfer **ptransfer)
{
+ struct r600_context *rctx = (struct r600_context*)ctx_;
+ struct compute_memory_pool *pool = rctx->screen->global_pool;
+ struct pipe_transfer *transfer = util_slab_alloc(&rctx->pool_transfers);
+ struct r600_resource_global* buffer =
+ (struct r600_resource_global*)resource;
+ uint32_t* map;
+
+ compute_memory_finalize_pending(pool, ctx_);
+
+ assert(resource->target == PIPE_BUFFER);
+
+ COMPUTE_DBG("* r600_compute_global_get_transfer()\n"
+ "level = %u, usage = %u, box(x = %u, y = %u, z = %u "
+ "width = %u, height = %u, depth = %u)\n", level, usage,
+ box->x, box->y, box->z, box->width, box->height,
+ box->depth);
+
+ transfer->resource = resource;
+ transfer->level = level;
+ transfer->usage = usage;
+ transfer->box = *box;
+ transfer->stride = 0;
+ transfer->layer_stride = 0;
+
assert(transfer->resource->target == PIPE_BUFFER);
assert(transfer->resource->bind & PIPE_BIND_GLOBAL);
assert(transfer->box.x >= 0);
assert(transfer->box.y == 0);
assert(transfer->box.z == 0);
- struct r600_context *ctx = (struct r600_context *)ctx_;
- struct r600_resource_global* buffer =
- (struct r600_resource_global*)transfer->resource;
-
- uint32_t* map;
///TODO: do it better, mapping is not possible if the pool is too big
COMPUTE_DBG("* r600_compute_global_transfer_map()\n");
- if (!(map = ctx->ws->buffer_map(buffer->chunk->pool->bo->cs_buf,
- ctx->cs, transfer->usage))) {
+ if (!(map = rctx->ws->buffer_map(buffer->chunk->pool->bo->cs_buf,
+ rctx->cs, transfer->usage))) {
+ util_slab_free(&rctx->pool_transfers, transfer);
return NULL;
}
+ *ptransfer = transfer;
+
COMPUTE_DBG("Buffer: %p + %u (buffer offset in global memory) "
"+ %u (box.x)\n", map, buffer->chunk->start_in_dw, transfer->box.x);
return ((char*)(map + buffer->chunk->start_in_dw)) + transfer->box.x;
COMPUTE_DBG("* r600_compute_global_transfer_unmap()\n");
ctx->ws->buffer_unmap(buffer->chunk->pool->bo->cs_buf);
-}
-
-struct pipe_transfer * r600_compute_global_get_transfer(
- struct pipe_context *ctx_,
- struct pipe_resource *resource,
- unsigned level,
- unsigned usage,
- const struct pipe_box *box)
-{
- struct r600_context *ctx = (struct r600_context *)ctx_;
- struct compute_memory_pool *pool = ctx->screen->global_pool;
-
- compute_memory_finalize_pending(pool, ctx_);
-
- assert(resource->target == PIPE_BUFFER);
- struct r600_context *rctx = (struct r600_context*)ctx_;
- struct pipe_transfer *transfer = util_slab_alloc(&rctx->pool_transfers);
-
- COMPUTE_DBG("* r600_compute_global_get_transfer()\n"
- "level = %u, usage = %u, box(x = %u, y = %u, z = %u "
- "width = %u, height = %u, depth = %u)\n", level, usage,
- box->x, box->y, box->z, box->width, box->height,
- box->depth);
-
- transfer->resource = resource;
- transfer->level = level;
- transfer->usage = usage;
- transfer->box = *box;
- transfer->stride = 0;
- transfer->layer_stride = 0;
- transfer->data = NULL;
-
- /* Note strides are zero, this is ok for buffers, but not for
- * textures 2d & higher at least.
- */
- return transfer;
-}
-
-void r600_compute_global_transfer_destroy(
- struct pipe_context *ctx_,
- struct pipe_transfer *transfer)
-{
- struct r600_context *rctx = (struct r600_context*)ctx_;
- util_slab_free(&rctx->pool_transfers, transfer);
+ util_slab_free(&ctx->pool_transfers, transfer);
}
void r600_compute_global_transfer_flush_region(
projects / mesa.git / blobdiff