struct r600_pipe_state * state = CALLOC_STRUCT(r600_pipe_state);
struct pipe_surface rat_templ;
+ struct r600_surface *surf;
+ struct r600_resource *res;
+ struct r600_context *rctx = pipe->ctx;
COMPUTE_DBG("bind rat: %i \n", id);
* of this driver. */
pipe->ctx->compute_cb_target_mask |= (0xf << (id * 4));
+ surf = (struct r600_surface*)pipe->ctx->framebuffer.cbufs[id];
+ res = (struct r600_resource*)surf->base.texture;
+
+ evergreen_init_color_surface(rctx, surf);
/* Get the CB register writes for the RAT */
- evergreen_cb(pipe->ctx, state, &pipe->ctx->framebuffer, id);
+ r600_pipe_state_add_reg_bo(state, R_028C60_CB_COLOR0_BASE + id * 0x3C,
+ surf->cb_color_base, res, RADEON_USAGE_READWRITE);
+ r600_pipe_state_add_reg(state, R_028C78_CB_COLOR0_DIM + id * 0x3C,
+ surf->cb_color_dim);
+ r600_pipe_state_add_reg_bo(state, R_028C70_CB_COLOR0_INFO + id * 0x3C,
+ surf->cb_color_info, res, RADEON_USAGE_READWRITE);
+ r600_pipe_state_add_reg(state, R_028C64_CB_COLOR0_PITCH + id * 0x3C,
+ surf->cb_color_pitch);
+ r600_pipe_state_add_reg(state, R_028C68_CB_COLOR0_SLICE + id * 0x3C,
+ surf->cb_color_slice);
+ r600_pipe_state_add_reg(state, R_028C6C_CB_COLOR0_VIEW + id * 0x3C,
+ surf->cb_color_view);
+ r600_pipe_state_add_reg_bo(state, R_028C74_CB_COLOR0_ATTRIB + id * 0x3C,
+ surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
/* Add the register blocks to the dirty list */
free(pipe->ctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
height = view->base.texture->height0;
depth = view->base.texture->depth0;
- pitch = align(tmp->pitch_in_blocks[0] *
+ pitch = align(tmp->surface.level[0].nblk_x *
util_format_get_blockwidth(tmp->real_format), 8);
array_mode = tmp->array_mode[0];
tile_type = tmp->tile_type;