struct r600_pipe_state * state = CALLOC_STRUCT(r600_pipe_state);
struct pipe_surface rat_templ;
+ struct r600_surface *surf;
+ struct r600_resource *res;
+ struct r600_context *rctx = pipe->ctx;
COMPUTE_DBG("bind rat: %i \n", id);
* XXX: I think this is a potential spot for bugs once we start doing
* GL interop. cb_target_mask may be modified in the 3D sections
* of this driver. */
- pipe->ctx->cb_target_mask |= (0xf << (id * 4));
+ pipe->ctx->compute_cb_target_mask |= (0xf << (id * 4));
+ surf = (struct r600_surface*)pipe->ctx->framebuffer.cbufs[id];
+ res = (struct r600_resource*)surf->base.texture;
+
+ evergreen_init_color_surface(rctx, surf);
/* Get the CB register writes for the RAT */
- evergreen_cb(pipe->ctx, state, &pipe->ctx->framebuffer, id);
+ r600_pipe_state_add_reg_bo(state, R_028C60_CB_COLOR0_BASE + id * 0x3C,
+ surf->cb_color_base, res, RADEON_USAGE_READWRITE);
+ r600_pipe_state_add_reg(state, R_028C78_CB_COLOR0_DIM + id * 0x3C,
+ surf->cb_color_dim);
+ r600_pipe_state_add_reg_bo(state, R_028C70_CB_COLOR0_INFO + id * 0x3C,
+ surf->cb_color_info, res, RADEON_USAGE_READWRITE);
+ r600_pipe_state_add_reg(state, R_028C64_CB_COLOR0_PITCH + id * 0x3C,
+ surf->cb_color_pitch);
+ r600_pipe_state_add_reg(state, R_028C68_CB_COLOR0_SLICE + id * 0x3C,
+ surf->cb_color_slice);
+ r600_pipe_state_add_reg(state, R_028C6C_CB_COLOR0_VIEW + id * 0x3C,
+ surf->cb_color_view);
+ r600_pipe_state_add_reg_bo(state, R_028C74_CB_COLOR0_ATTRIB + id * 0x3C,
+ surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
/* Add the register blocks to the dirty list */
free(pipe->ctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
r600_context_pipe_state_set(pipe->ctx, state);
}
-void evergreen_set_lds(
- struct r600_pipe_compute *pipe,
- int num_lds,
- int size,
- int num_waves)
-{
- struct evergreen_compute_resource* res =
- get_empty_res(pipe, COMPUTE_RESOURCE_LDS, 0);
-
- if (pipe->ctx->chip_class < CAYMAN) {
- evergreen_reg_set(res, R_008E2C_SQ_LDS_RESOURCE_MGMT,
- S_008E2C_NUM_LS_LDS(num_lds));
- } else {
- evergreen_reg_set(res, CM_R_0286FC_SPI_LDS_MGMT,
- S_0286FC_NUM_LS_LDS(num_lds));
- }
- evergreen_reg_set(res, CM_R_0288E8_SQ_LDS_ALLOC, size | num_waves << 14);
-}
-
void evergreen_set_gds(
struct r600_pipe_compute *pipe,
uint32_t addr,
}
}
-void evergreen_set_vtx_resource(
- struct r600_pipe_compute *pipe,
- struct r600_resource* bo,
- int id, uint64_t offset, int writable)
-{
- assert(id < 16);
- uint32_t sq_vtx_constant_word2, sq_vtx_constant_word3, sq_vtx_constant_word4;
- struct number_type_and_format fmt;
- uint64_t va;
-
- fmt.format = 0;
-
- assert(bo->b.b.height0 <= 1);
- assert(bo->b.b.depth0 <= 1);
-
- int e = evergreen_compute_get_gpu_format(&fmt, bo);
-
- assert(e && "unknown format");
-
- struct evergreen_compute_resource* res =
- get_empty_res(pipe, COMPUTE_RESOURCE_VERT, id);
-
- unsigned size = bo->b.b.width0;
- unsigned stride = 1;
-
-// size = (size * util_format_get_blockwidth(bo->b.b.b.format) *
-// util_format_get_blocksize(bo->b.b.b.format));
-
- va = r600_resource_va(&pipe->ctx->screen->screen, &bo->b.b) + offset;
-
- COMPUTE_DBG("id: %i vtx size: %i byte, width0: %i elem\n",
- id, size, bo->b.b.width0);
-
- sq_vtx_constant_word2 =
- S_030008_BASE_ADDRESS_HI(va >> 32) |
- S_030008_STRIDE(stride) |
- S_030008_DATA_FORMAT(fmt.format) |
- S_030008_NUM_FORMAT_ALL(fmt.num_format_all) |
- S_030008_ENDIAN_SWAP(0);
-
- COMPUTE_DBG("%08X %i %i %i %i\n", sq_vtx_constant_word2, offset,
- stride, fmt.format, fmt.num_format_all);
-
- sq_vtx_constant_word3 =
- S_03000C_DST_SEL_X(0) |
- S_03000C_DST_SEL_Y(1) |
- S_03000C_DST_SEL_Z(2) |
- S_03000C_DST_SEL_W(3);
-
- sq_vtx_constant_word4 = 0;
-
- evergreen_emit_raw_value(res, PKT3C(PKT3_SET_RESOURCE, 8, 0));
- evergreen_emit_raw_value(res, (id+816)*32 >> 2);
- evergreen_emit_raw_value(res, (unsigned)((va) & 0xffffffff));
- evergreen_emit_raw_value(res, size - 1);
- evergreen_emit_raw_value(res, sq_vtx_constant_word2);
- evergreen_emit_raw_value(res, sq_vtx_constant_word3);
- evergreen_emit_raw_value(res, sq_vtx_constant_word4);
- evergreen_emit_raw_value(res, 0);
- evergreen_emit_raw_value(res, 0);
- evergreen_emit_raw_value(res, S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
-
- res->bo = bo;
-
- if (writable) {
- res->usage = RADEON_USAGE_READWRITE;
- }
- else {
- res->usage = RADEON_USAGE_READ;
- }
-
- res->coher_bo_size = size;
-
- r600_inval_vertex_cache(pipe->ctx);
- /* XXX: Do we really need to invalidate the texture cache here?
- * r600_inval_vertex_cache() will invalidate the texture cache
- * if the chip does not have a vertex cache.
- */
- r600_inval_texture_cache(pipe->ctx);
-}
-
void evergreen_set_tex_resource(
struct r600_pipe_compute *pipe,
struct r600_pipe_sampler_view* view,
{
struct evergreen_compute_resource* res =
get_empty_res(pipe, COMPUTE_RESOURCE_TEX, id);
- struct r600_resource_texture *tmp =
- (struct r600_resource_texture*)view->base.texture;
+ struct r600_texture *tmp =
+ (struct r600_texture*)view->base.texture;
unsigned format, endian;
uint32_t word4 = 0, yuv_format = 0, pitch = 0;
height = view->base.texture->height0;
depth = view->base.texture->depth0;
- pitch = align(tmp->pitch_in_blocks[0] *
- util_format_get_blockwidth(tmp->real_format), 8);
+ pitch = align(tmp->surface.level[0].nblk_x *
+ util_format_get_blockwidth(tmp->resource.b.b.format), 8);
array_mode = tmp->array_mode[0];
tile_type = tmp->tile_type;
evergreen_emit_raw_value(res, (S_030004_TEX_HEIGHT(height - 1) |
S_030004_TEX_DEPTH(depth - 1) |
S_030004_ARRAY_MODE(array_mode)));
- evergreen_emit_raw_value(res, tmp->offset[0] >> 8);
- evergreen_emit_raw_value(res, tmp->offset[0] >> 8);
+ evergreen_emit_raw_value(res, tmp->surface.level[0].offset >> 8);
+ evergreen_emit_raw_value(res, tmp->surface.level[0].offset >> 8);
evergreen_emit_raw_value(res, (word4 |
S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
S_030010_ENDIAN_SWAP(endian) |
res->usage = RADEON_USAGE_READ;
- res->coher_bo_size = tmp->offset[0] + util_format_get_blockwidth(tmp->real_format)*view->base.texture->width0*height*depth;
+ res->coher_bo_size = tmp->surface.level[0].offset +
+ util_format_get_blockwidth(tmp->resource.b.b.format) *
+ view->base.texture->width0*height*depth;
- r600_inval_texture_cache(pipe->ctx);
+ pipe->ctx->flags |= R600_CONTEXT_TEX_FLUSH;
evergreen_emit_force_reloc(res);
evergreen_emit_force_reloc(res);
res->usage = RADEON_USAGE_READ;
res->coher_bo_size = size;
- r600_inval_shader_cache(pipe->ctx);
+ pipe->ctx->flags |= R600_CONTEXT_SHADERCONST_FLUSH;
}
struct r600_resource* r600_compute_buffer_alloc_vram(
projects / mesa.git / blobdiff