radeonsi: implement TC L2 write-back (flush) without cache invalidation

[mesa.git] / src / gallium / drivers / r600 / evergreen_compute_internal.h

diff --git a/src/gallium/drivers/r600/evergreen_compute_internal.h b/src/gallium/drivers/r600/evergreen_compute_internal.h
index 0929d8dcf270eb1620f31f1a3bcbd4aebfbdc0b5..e6ff7609aea2f39e75e7006899e74e16b1ae1be9 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_compute_internal.h
+++ b/src/gallium/drivers/r600/evergreen_compute_internal.h
@@ -26,23 +26,18 @@
 #define EVERGREEN_COMPUTE_INTERNAL_H
 
 #include "r600_asm.h"
-
-struct r600_kernel {
-       unsigned count;
 #ifdef HAVE_OPENCL
-       LLVMModuleRef llvm_module;
+#include "radeon/radeon_llvm.h"
+#include <llvm-c/Core.h>
 #endif
-       struct r600_resource *code_bo;
-       struct r600_bytecode bc;
-};
 
 struct r600_pipe_compute {
        struct r600_context *ctx;
 
-       unsigned num_kernels;
-       struct r600_kernel *kernels;
+       struct radeon_shader_binary binary;
+       struct r600_resource *code_bo;
+       struct r600_bytecode bc;
 
-       struct r600_kernel *active_kernel;
        unsigned local_size;
        unsigned private_size;
        unsigned input_size;