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r600g: Close a memory leak of llvm byte streams
[mesa.git] / src / gallium / drivers / r600 / evergreen_hw_context.c
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index 24c504dc2e18672c2fb3608403671f5166a86a2e..0c2159a677c25f4d36e78bff9e6568f839cbea9c 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -27,21 +27,11 @@
 #include "evergreend.h"
 #include "util/u_memory.h"
 
-static const struct r600_reg evergreen_config_reg_list[] = {
-       {R_008958_VGT_PRIMITIVE_TYPE, 0},
-};
-
-
 static const struct r600_reg cayman_config_reg_list[] = {
-       {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
        {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
        {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
 };
 
-static const struct r600_reg evergreen_ctl_const_list[] = {
-       {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
-};
-
 static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028008_DB_DEPTH_VIEW, 0, 0},
        {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
@@ -69,35 +59,6 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
        {R_028350_SX_MISC, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
-       {R_028408_VGT_INDX_OFFSET, 0, 0},
-       {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
-       {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
-       {GROUP_FORCE_NEW_BLOCK, 0, 0},
-       {R_0285BC_PA_CL_UCP0_X, 0, 0},
-       {R_0285C0_PA_CL_UCP0_Y, 0, 0},
-       {R_0285C4_PA_CL_UCP0_Z, 0, 0},
-       {R_0285C8_PA_CL_UCP0_W, 0, 0},
-       {R_0285CC_PA_CL_UCP1_X, 0, 0},
-       {R_0285D0_PA_CL_UCP1_Y, 0, 0},
-       {R_0285D4_PA_CL_UCP1_Z, 0, 0},
-       {R_0285D8_PA_CL_UCP1_W, 0, 0},
-       {R_0285DC_PA_CL_UCP2_X, 0, 0},
-       {R_0285E0_PA_CL_UCP2_Y, 0, 0},
-       {R_0285E4_PA_CL_UCP2_Z, 0, 0},
-       {R_0285E8_PA_CL_UCP2_W, 0, 0},
-       {R_0285EC_PA_CL_UCP3_X, 0, 0},
-       {R_0285F0_PA_CL_UCP3_Y, 0, 0},
-       {R_0285F4_PA_CL_UCP3_Z, 0, 0},
-       {R_0285F8_PA_CL_UCP3_W, 0, 0},
-       {R_0285FC_PA_CL_UCP4_X, 0, 0},
-       {R_028600_PA_CL_UCP4_Y, 0, 0},
-       {R_028604_PA_CL_UCP4_Z, 0, 0},
-       {R_028608_PA_CL_UCP4_W, 0, 0},
-       {R_02860C_PA_CL_UCP5_X, 0, 0},
-       {R_028610_PA_CL_UCP5_Y, 0, 0},
-       {R_028614_PA_CL_UCP5_Z, 0, 0},
-       {R_028618_PA_CL_UCP5_W, 0, 0},
-       {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
        {R_028620_SPI_VS_OUT_ID_1, 0, 0},
        {R_028624_SPI_VS_OUT_ID_2, 0, 0},
@@ -162,9 +123,7 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028800_DB_DEPTH_CONTROL, 0, 0},
        {R_02880C_DB_SHADER_CONTROL, 0, 0},
        {R_028808_CB_COLOR_CONTROL, 0, 0},
-       {R_028810_PA_CL_CLIP_CNTL, 0, 0},
        {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
-       {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
        {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
        {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
        {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
@@ -175,9 +134,7 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028A00_PA_SU_POINT_SIZE, 0, 0},
        {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
        {R_028A08_PA_SU_LINE_CNTL, 0, 0},
-       {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
        {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
-       {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
        {R_028ABC_DB_HTILE_SURFACE, 0, 0},
        {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
        {R_028B70_DB_ALPHA_TO_MASK, 0, 0},
@@ -388,34 +345,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
        {R_028350_SX_MISC, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
-       {R_028408_VGT_INDX_OFFSET, 0, 0},
-       {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
-       {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
-       {GROUP_FORCE_NEW_BLOCK, 0, 0},
-       {R_0285BC_PA_CL_UCP0_X, 0, 0},
-       {R_0285C0_PA_CL_UCP0_Y, 0, 0},
-       {R_0285C4_PA_CL_UCP0_Z, 0, 0},
-       {R_0285C8_PA_CL_UCP0_W, 0, 0},
-       {R_0285CC_PA_CL_UCP1_X, 0, 0},
-       {R_0285D0_PA_CL_UCP1_Y, 0, 0},
-       {R_0285D4_PA_CL_UCP1_Z, 0, 0},
-       {R_0285D8_PA_CL_UCP1_W, 0, 0},
-       {R_0285DC_PA_CL_UCP2_X, 0, 0},
-       {R_0285E0_PA_CL_UCP2_Y, 0, 0},
-       {R_0285E4_PA_CL_UCP2_Z, 0, 0},
-       {R_0285E8_PA_CL_UCP2_W, 0, 0},
-       {R_0285EC_PA_CL_UCP3_X, 0, 0},
-       {R_0285F0_PA_CL_UCP3_Y, 0, 0},
-       {R_0285F4_PA_CL_UCP3_Z, 0, 0},
-       {R_0285F8_PA_CL_UCP3_W, 0, 0},
-       {R_0285FC_PA_CL_UCP4_X, 0, 0},
-       {R_028600_PA_CL_UCP4_Y, 0, 0},
-       {R_028604_PA_CL_UCP4_Z, 0, 0},
-       {R_028608_PA_CL_UCP4_W, 0, 0},
-       {R_02860C_PA_CL_UCP5_X, 0, 0},
-       {R_028610_PA_CL_UCP5_Y, 0, 0},
-       {R_028614_PA_CL_UCP5_Z, 0, 0},
-       {R_028618_PA_CL_UCP5_W, 0, 0},
        {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
        {R_028620_SPI_VS_OUT_ID_1, 0, 0},
        {R_028624_SPI_VS_OUT_ID_2, 0, 0},
@@ -479,9 +408,7 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {CM_R_028804_DB_EQAA},
        {R_028808_CB_COLOR_CONTROL, 0, 0},
        {R_02880C_DB_SHADER_CONTROL, 0, 0},
-       {R_028810_PA_CL_CLIP_CNTL, 0, 0},
        {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
-       {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
        {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0},
        {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
        {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
@@ -502,9 +429,7 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028A00_PA_SU_POINT_SIZE, 0, 0},
        {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
        {R_028A08_PA_SU_LINE_CNTL, 0, 0},
-       {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
        {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
-       {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
        {R_028ABC_DB_HTILE_SURFACE, 0, 0},
        {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
        {R_028B70_DB_ALPHA_TO_MASK, 0, 0},
@@ -711,15 +636,12 @@ static int evergreen_loop_const_init(struct r600_context *ctx, uint32_t offset)
 
 int evergreen_context_init(struct r600_context *ctx)
 {
-       int r;
+       int r = 0;
 
        /* add blocks */
        if (ctx->family >= CHIP_CAYMAN)
                r = r600_context_add_block(ctx, cayman_config_reg_list,
                                           Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
-       else
-               r = r600_context_add_block(ctx, evergreen_config_reg_list,
-                                          Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
        if (r)
                goto out_err;
        if (ctx->family >= CHIP_CAYMAN)
@@ -730,10 +652,6 @@ int evergreen_context_init(struct r600_context *ctx)
                                           Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
        if (r)
                goto out_err;
-       r = r600_context_add_block(ctx, evergreen_ctl_const_list,
-                                  Elements(evergreen_ctl_const_list), PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET);
-       if (r)
-               goto out_err;
 
        /* PS loop const */
        evergreen_loop_const_init(ctx, 0);