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r600g: Close a memory leak of llvm byte streams
[mesa.git] / src / gallium / drivers / r600 / evergreen_hw_context.c
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index f0c4ff7a482ca2bc6d644e8fc284cc40918acfde..0c2159a677c25f4d36e78bff9e6568f839cbea9c 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -27,21 +27,11 @@
 #include "evergreend.h"
 #include "util/u_memory.h"
 
-static const struct r600_reg evergreen_config_reg_list[] = {
-       {R_008958_VGT_PRIMITIVE_TYPE, 0},
-};
-
-
 static const struct r600_reg cayman_config_reg_list[] = {
-       {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
        {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
        {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
 };
 
-static const struct r600_reg evergreen_ctl_const_list[] = {
-       {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
-};
-
 static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028008_DB_DEPTH_VIEW, 0, 0},
        {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
@@ -69,47 +59,6 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
        {R_028350_SX_MISC, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
-       {R_028408_VGT_INDX_OFFSET, 0, 0},
-       {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
-       {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
-       {GROUP_FORCE_NEW_BLOCK, 0, 0},
-       {R_028414_CB_BLEND_RED, 0, 0},
-       {R_028418_CB_BLEND_GREEN, 0, 0},
-       {R_02841C_CB_BLEND_BLUE, 0, 0},
-       {R_028420_CB_BLEND_ALPHA, 0, 0},
-       {R_028430_DB_STENCILREFMASK, 0, 0},
-       {R_028434_DB_STENCILREFMASK_BF, 0, 0},
-       {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
-       {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
-       {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
-       {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
-       {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
-       {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
-       {R_0285BC_PA_CL_UCP0_X, 0, 0},
-       {R_0285C0_PA_CL_UCP0_Y, 0, 0},
-       {R_0285C4_PA_CL_UCP0_Z, 0, 0},
-       {R_0285C8_PA_CL_UCP0_W, 0, 0},
-       {R_0285CC_PA_CL_UCP1_X, 0, 0},
-       {R_0285D0_PA_CL_UCP1_Y, 0, 0},
-       {R_0285D4_PA_CL_UCP1_Z, 0, 0},
-       {R_0285D8_PA_CL_UCP1_W, 0, 0},
-       {R_0285DC_PA_CL_UCP2_X, 0, 0},
-       {R_0285E0_PA_CL_UCP2_Y, 0, 0},
-       {R_0285E4_PA_CL_UCP2_Z, 0, 0},
-       {R_0285E8_PA_CL_UCP2_W, 0, 0},
-       {R_0285EC_PA_CL_UCP3_X, 0, 0},
-       {R_0285F0_PA_CL_UCP3_Y, 0, 0},
-       {R_0285F4_PA_CL_UCP3_Z, 0, 0},
-       {R_0285F8_PA_CL_UCP3_W, 0, 0},
-       {R_0285FC_PA_CL_UCP4_X, 0, 0},
-       {R_028600_PA_CL_UCP4_Y, 0, 0},
-       {R_028604_PA_CL_UCP4_Z, 0, 0},
-       {R_028608_PA_CL_UCP4_W, 0, 0},
-       {R_02860C_PA_CL_UCP5_X, 0, 0},
-       {R_028610_PA_CL_UCP5_Y, 0, 0},
-       {R_028614_PA_CL_UCP5_Z, 0, 0},
-       {R_028618_PA_CL_UCP5_W, 0, 0},
-       {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
        {R_028620_SPI_VS_OUT_ID_1, 0, 0},
        {R_028624_SPI_VS_OUT_ID_2, 0, 0},
@@ -174,9 +123,7 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028800_DB_DEPTH_CONTROL, 0, 0},
        {R_02880C_DB_SHADER_CONTROL, 0, 0},
        {R_028808_CB_COLOR_CONTROL, 0, 0},
-       {R_028810_PA_CL_CLIP_CNTL, 0, 0},
        {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
-       {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
        {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
        {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
        {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
@@ -187,9 +134,7 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028A00_PA_SU_POINT_SIZE, 0, 0},
        {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
        {R_028A08_PA_SU_LINE_CNTL, 0, 0},
-       {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
        {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
-       {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
        {R_028ABC_DB_HTILE_SURFACE, 0, 0},
        {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
        {R_028B70_DB_ALPHA_TO_MASK, 0, 0},
@@ -219,6 +164,14 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
        {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028C78_CB_COLOR0_DIM, 0, 0},
+       {R_028C7C_CB_COLOR0_CMASK, REG_FLAG_NEED_BO},
+       {R_028C80_CB_COLOR0_CMASK_SLICE},
+       {R_028C84_CB_COLOR0_FMASK, REG_FLAG_NEED_BO},
+       {R_028C88_CB_COLOR0_FMASK_SLICE},
+       {R_028C8C_CB_COLOR0_CLEAR_WORD0},
+       {R_028C90_CB_COLOR0_CLEAR_WORD1},
+       {R_028C94_CB_COLOR0_CLEAR_WORD2},
+       {R_028C98_CB_COLOR0_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0},
        {R_028CA0_CB_COLOR1_PITCH, 0, 0},
@@ -227,6 +180,14 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
        {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028CB4_CB_COLOR1_DIM, 0, 0},
+       {R_028CB8_CB_COLOR1_CMASK, REG_FLAG_NEED_BO, 0},
+       {R_028CBC_CB_COLOR1_CMASK_SLICE, 0, 0},
+       {R_028CC0_CB_COLOR1_FMASK, REG_FLAG_NEED_BO, 0},
+       {R_028CC4_CB_COLOR1_FMASK_SLICE, 0, 0},
+       {R_028CC8_CB_COLOR1_CLEAR_WORD0},
+       {R_028CCC_CB_COLOR1_CLEAR_WORD1},
+       {R_028CD0_CB_COLOR1_CLEAR_WORD2},
+       {R_028CD4_CB_COLOR1_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0},
        {R_028CDC_CB_COLOR2_PITCH, 0, 0},
@@ -235,6 +196,14 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
        {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028CF0_CB_COLOR2_DIM, 0, 0},
+       {R_028CF4_CB_COLOR2_CMASK, REG_FLAG_NEED_BO, 0},
+       {R_028CF8_CB_COLOR2_CMASK_SLICE, 0, 0},
+       {R_028CFC_CB_COLOR2_FMASK, REG_FLAG_NEED_BO, 0},
+       {R_028D00_CB_COLOR2_FMASK_SLICE, 0, 0},
+       {R_028D04_CB_COLOR2_CLEAR_WORD0},
+       {R_028D08_CB_COLOR2_CLEAR_WORD1},
+       {R_028D0C_CB_COLOR2_CLEAR_WORD2},
+       {R_028D10_CB_COLOR2_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0},
        {R_028D18_CB_COLOR3_PITCH, 0, 0},
@@ -243,6 +212,14 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
        {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028D2C_CB_COLOR3_DIM, 0, 0},
+       {R_028D30_CB_COLOR3_CMASK, REG_FLAG_NEED_BO},
+       {R_028D34_CB_COLOR3_CMASK_SLICE},
+       {R_028D38_CB_COLOR3_FMASK, REG_FLAG_NEED_BO},
+       {R_028D3C_CB_COLOR3_FMASK_SLICE},
+       {R_028D40_CB_COLOR3_CLEAR_WORD0},
+       {R_028D44_CB_COLOR3_CLEAR_WORD1},
+       {R_028D48_CB_COLOR3_CLEAR_WORD2},
+       {R_028D4C_CB_COLOR3_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0},
        {R_028D54_CB_COLOR4_PITCH, 0, 0},
@@ -251,6 +228,14 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
        {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028D68_CB_COLOR4_DIM, 0, 0},
+       {R_028D6C_CB_COLOR4_CMASK, REG_FLAG_NEED_BO},
+       {R_028D70_CB_COLOR4_CMASK_SLICE},
+       {R_028D74_CB_COLOR4_FMASK, REG_FLAG_NEED_BO},
+       {R_028D78_CB_COLOR4_FMASK_SLICE},
+       {R_028D7C_CB_COLOR4_CLEAR_WORD0},
+       {R_028D80_CB_COLOR4_CLEAR_WORD1},
+       {R_028D84_CB_COLOR4_CLEAR_WORD2},
+       {R_028D88_CB_COLOR4_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0},
        {R_028D90_CB_COLOR5_PITCH, 0, 0},
@@ -259,6 +244,14 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
        {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028DA4_CB_COLOR5_DIM, 0, 0},
+       {R_028DA8_CB_COLOR5_CMASK, REG_FLAG_NEED_BO},
+       {R_028DAC_CB_COLOR5_CMASK_SLICE},
+       {R_028DB0_CB_COLOR5_FMASK, REG_FLAG_NEED_BO},
+       {R_028DB4_CB_COLOR5_FMASK_SLICE},
+       {R_028DB8_CB_COLOR5_CLEAR_WORD0},
+       {R_028DBC_CB_COLOR5_CLEAR_WORD1},
+       {R_028DC0_CB_COLOR5_CLEAR_WORD2},
+       {R_028DC4_CB_COLOR5_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0},
        {R_028DCC_CB_COLOR6_PITCH, 0, 0},
@@ -267,6 +260,14 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
        {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028DE0_CB_COLOR6_DIM, 0, 0},
+       {R_028DE4_CB_COLOR6_CMASK, REG_FLAG_NEED_BO},
+       {R_028DE8_CB_COLOR6_CMASK_SLICE},
+       {R_028DEC_CB_COLOR6_FMASK, REG_FLAG_NEED_BO},
+       {R_028DF0_CB_COLOR6_FMASK_SLICE},
+       {R_028DF4_CB_COLOR6_CLEAR_WORD0},
+       {R_028DF8_CB_COLOR6_CLEAR_WORD1},
+       {R_028DFC_CB_COLOR6_CLEAR_WORD2},
+       {R_028E00_CB_COLOR6_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0},
        {R_028E08_CB_COLOR7_PITCH, 0, 0},
@@ -275,6 +276,14 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
        {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028E1C_CB_COLOR7_DIM, 0, 0},
+       {R_028E20_CB_COLOR7_CMASK, REG_FLAG_NEED_BO},
+       {R_028E24_CB_COLOR7_CMASK_SLICE},
+       {R_028E28_CB_COLOR7_FMASK, REG_FLAG_NEED_BO},
+       {R_028E2C_CB_COLOR7_FMASK_SLICE},
+       {R_028E30_CB_COLOR7_CLEAR_WORD0},
+       {R_028E34_CB_COLOR7_CLEAR_WORD1},
+       {R_028E38_CB_COLOR7_CLEAR_WORD2},
+       {R_028E3C_CB_COLOR7_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0},
        {R_028E44_CB_COLOR8_PITCH, 0, 0},
@@ -336,46 +345,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
        {R_028350_SX_MISC, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
-       {R_028408_VGT_INDX_OFFSET, 0, 0},
-       {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
-       {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
-       {GROUP_FORCE_NEW_BLOCK, 0, 0},
-       {R_028414_CB_BLEND_RED, 0, 0},
-       {R_028418_CB_BLEND_GREEN, 0, 0},
-       {R_02841C_CB_BLEND_BLUE, 0, 0},
-       {R_028420_CB_BLEND_ALPHA, 0, 0},
-       {R_028430_DB_STENCILREFMASK, 0, 0},
-       {R_028434_DB_STENCILREFMASK_BF, 0, 0},
-       {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
-       {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
-       {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
-       {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
-       {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
-       {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
-       {R_0285BC_PA_CL_UCP0_X, 0, 0},
-       {R_0285C0_PA_CL_UCP0_Y, 0, 0},
-       {R_0285C4_PA_CL_UCP0_Z, 0, 0},
-       {R_0285C8_PA_CL_UCP0_W, 0, 0},
-       {R_0285CC_PA_CL_UCP1_X, 0, 0},
-       {R_0285D0_PA_CL_UCP1_Y, 0, 0},
-       {R_0285D4_PA_CL_UCP1_Z, 0, 0},
-       {R_0285D8_PA_CL_UCP1_W, 0, 0},
-       {R_0285DC_PA_CL_UCP2_X, 0, 0},
-       {R_0285E0_PA_CL_UCP2_Y, 0, 0},
-       {R_0285E4_PA_CL_UCP2_Z, 0, 0},
-       {R_0285E8_PA_CL_UCP2_W, 0, 0},
-       {R_0285EC_PA_CL_UCP3_X, 0, 0},
-       {R_0285F0_PA_CL_UCP3_Y, 0, 0},
-       {R_0285F4_PA_CL_UCP3_Z, 0, 0},
-       {R_0285F8_PA_CL_UCP3_W, 0, 0},
-       {R_0285FC_PA_CL_UCP4_X, 0, 0},
-       {R_028600_PA_CL_UCP4_Y, 0, 0},
-       {R_028604_PA_CL_UCP4_Z, 0, 0},
-       {R_028608_PA_CL_UCP4_W, 0, 0},
-       {R_02860C_PA_CL_UCP5_X, 0, 0},
-       {R_028610_PA_CL_UCP5_Y, 0, 0},
-       {R_028614_PA_CL_UCP5_Z, 0, 0},
-       {R_028618_PA_CL_UCP5_W, 0, 0},
        {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
        {R_028620_SPI_VS_OUT_ID_1, 0, 0},
        {R_028624_SPI_VS_OUT_ID_2, 0, 0},
@@ -436,11 +405,10 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028798_CB_BLEND6_CONTROL, 0, 0},
        {R_02879C_CB_BLEND7_CONTROL, 0, 0},
        {R_028800_DB_DEPTH_CONTROL, 0, 0},
+       {CM_R_028804_DB_EQAA},
        {R_028808_CB_COLOR_CONTROL, 0, 0},
        {R_02880C_DB_SHADER_CONTROL, 0, 0},
-       {R_028810_PA_CL_CLIP_CNTL, 0, 0},
        {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
-       {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
        {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0},
        {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
        {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
@@ -461,9 +429,7 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028A00_PA_SU_POINT_SIZE, 0, 0},
        {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
        {R_028A08_PA_SU_LINE_CNTL, 0, 0},
-       {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
        {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
-       {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
        {R_028ABC_DB_HTILE_SURFACE, 0, 0},
        {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
        {R_028B70_DB_ALPHA_TO_MASK, 0, 0},
@@ -500,6 +466,14 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
        {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028C78_CB_COLOR0_DIM, 0, 0},
+       {R_028C7C_CB_COLOR0_CMASK, REG_FLAG_NEED_BO},
+       {R_028C80_CB_COLOR0_CMASK_SLICE},
+       {R_028C84_CB_COLOR0_FMASK, REG_FLAG_NEED_BO},
+       {R_028C88_CB_COLOR0_FMASK_SLICE},
+       {R_028C8C_CB_COLOR0_CLEAR_WORD0},
+       {R_028C90_CB_COLOR0_CLEAR_WORD1},
+       {R_028C94_CB_COLOR0_CLEAR_WORD2},
+       {R_028C98_CB_COLOR0_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0},
        {R_028CA0_CB_COLOR1_PITCH, 0, 0},
@@ -508,6 +482,14 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
        {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028CB4_CB_COLOR1_DIM, 0, 0},
+       {R_028CB8_CB_COLOR1_CMASK, REG_FLAG_NEED_BO, 0},
+       {R_028CBC_CB_COLOR1_CMASK_SLICE, 0, 0},
+       {R_028CC0_CB_COLOR1_FMASK, REG_FLAG_NEED_BO, 0},
+       {R_028CC4_CB_COLOR1_FMASK_SLICE, 0, 0},
+       {R_028CC8_CB_COLOR1_CLEAR_WORD0},
+       {R_028CCC_CB_COLOR1_CLEAR_WORD1},
+       {R_028CD0_CB_COLOR1_CLEAR_WORD2},
+       {R_028CD4_CB_COLOR1_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0},
        {R_028CDC_CB_COLOR2_PITCH, 0, 0},
@@ -516,6 +498,14 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
        {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028CF0_CB_COLOR2_DIM, 0, 0},
+       {R_028CF4_CB_COLOR2_CMASK, REG_FLAG_NEED_BO, 0},
+       {R_028CF8_CB_COLOR2_CMASK_SLICE, 0, 0},
+       {R_028CFC_CB_COLOR2_FMASK, REG_FLAG_NEED_BO, 0},
+       {R_028D00_CB_COLOR2_FMASK_SLICE, 0, 0},
+       {R_028D04_CB_COLOR2_CLEAR_WORD0},
+       {R_028D08_CB_COLOR2_CLEAR_WORD1},
+       {R_028D0C_CB_COLOR2_CLEAR_WORD2},
+       {R_028D10_CB_COLOR2_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0},
        {R_028D18_CB_COLOR3_PITCH, 0, 0},
@@ -524,6 +514,14 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
        {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028D2C_CB_COLOR3_DIM, 0, 0},
+       {R_028D30_CB_COLOR3_CMASK, REG_FLAG_NEED_BO},
+       {R_028D34_CB_COLOR3_CMASK_SLICE},
+       {R_028D38_CB_COLOR3_FMASK, REG_FLAG_NEED_BO},
+       {R_028D3C_CB_COLOR3_FMASK_SLICE},
+       {R_028D40_CB_COLOR3_CLEAR_WORD0},
+       {R_028D44_CB_COLOR3_CLEAR_WORD1},
+       {R_028D48_CB_COLOR3_CLEAR_WORD2},
+       {R_028D4C_CB_COLOR3_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0},
        {R_028D54_CB_COLOR4_PITCH, 0, 0},
@@ -532,6 +530,14 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
        {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028D68_CB_COLOR4_DIM, 0, 0},
+       {R_028D6C_CB_COLOR4_CMASK, REG_FLAG_NEED_BO},
+       {R_028D70_CB_COLOR4_CMASK_SLICE},
+       {R_028D74_CB_COLOR4_FMASK, REG_FLAG_NEED_BO},
+       {R_028D78_CB_COLOR4_FMASK_SLICE},
+       {R_028D7C_CB_COLOR4_CLEAR_WORD0},
+       {R_028D80_CB_COLOR4_CLEAR_WORD1},
+       {R_028D84_CB_COLOR4_CLEAR_WORD2},
+       {R_028D88_CB_COLOR4_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0},
        {R_028D90_CB_COLOR5_PITCH, 0, 0},
@@ -540,6 +546,14 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
        {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028DA4_CB_COLOR5_DIM, 0, 0},
+       {R_028DA8_CB_COLOR5_CMASK, REG_FLAG_NEED_BO},
+       {R_028DAC_CB_COLOR5_CMASK_SLICE},
+       {R_028DB0_CB_COLOR5_FMASK, REG_FLAG_NEED_BO},
+       {R_028DB4_CB_COLOR5_FMASK_SLICE},
+       {R_028DB8_CB_COLOR5_CLEAR_WORD0},
+       {R_028DBC_CB_COLOR5_CLEAR_WORD1},
+       {R_028DC0_CB_COLOR5_CLEAR_WORD2},
+       {R_028DC4_CB_COLOR5_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0},
        {R_028DCC_CB_COLOR6_PITCH, 0, 0},
@@ -548,6 +562,14 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
        {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028DE0_CB_COLOR6_DIM, 0, 0},
+       {R_028DE4_CB_COLOR6_CMASK, REG_FLAG_NEED_BO},
+       {R_028DE8_CB_COLOR6_CMASK_SLICE},
+       {R_028DEC_CB_COLOR6_FMASK, REG_FLAG_NEED_BO},
+       {R_028DF0_CB_COLOR6_FMASK_SLICE},
+       {R_028DF4_CB_COLOR6_CLEAR_WORD0},
+       {R_028DF8_CB_COLOR6_CLEAR_WORD1},
+       {R_028DFC_CB_COLOR6_CLEAR_WORD2},
+       {R_028E00_CB_COLOR6_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0},
        {R_028E08_CB_COLOR7_PITCH, 0, 0},
@@ -556,6 +578,14 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
        {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0},
        {R_028E1C_CB_COLOR7_DIM, 0, 0},
+       {R_028E20_CB_COLOR7_CMASK, REG_FLAG_NEED_BO},
+       {R_028E24_CB_COLOR7_CMASK_SLICE},
+       {R_028E28_CB_COLOR7_FMASK, REG_FLAG_NEED_BO},
+       {R_028E2C_CB_COLOR7_FMASK_SLICE},
+       {R_028E30_CB_COLOR7_CLEAR_WORD0},
+       {R_028E34_CB_COLOR7_CLEAR_WORD1},
+       {R_028E38_CB_COLOR7_CLEAR_WORD2},
+       {R_028E3C_CB_COLOR7_CLEAR_WORD3},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0},
        {R_028E44_CB_COLOR8_PITCH, 0, 0},
@@ -606,15 +636,12 @@ static int evergreen_loop_const_init(struct r600_context *ctx, uint32_t offset)
 
 int evergreen_context_init(struct r600_context *ctx)
 {
-       int r;
+       int r = 0;
 
        /* add blocks */
        if (ctx->family >= CHIP_CAYMAN)
                r = r600_context_add_block(ctx, cayman_config_reg_list,
                                           Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
-       else
-               r = r600_context_add_block(ctx, evergreen_config_reg_list,
-                                          Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
        if (r)
                goto out_err;
        if (ctx->family >= CHIP_CAYMAN)
@@ -625,10 +652,6 @@ int evergreen_context_init(struct r600_context *ctx)
                                           Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
        if (r)
                goto out_err;
-       r = r600_context_add_block(ctx, evergreen_ctl_const_list,
-                                  Elements(evergreen_ctl_const_list), PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET);
-       if (r)
-               goto out_err;
 
        /* PS loop const */
        evergreen_loop_const_init(ctx, 0);