r600g: atomize clip state

[mesa.git] / src / gallium / drivers / r600 / evergreen_hw_context.c

diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index b2ea7e238dd665fd93b7dff51c01da5dbfcd6c2f..7a3d08854a4afef962381f14b76679a07b1bb3bd 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -73,43 +73,6 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
        {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
-       {R_028414_CB_BLEND_RED, 0, 0},
-       {R_028418_CB_BLEND_GREEN, 0, 0},
-       {R_02841C_CB_BLEND_BLUE, 0, 0},
-       {R_028420_CB_BLEND_ALPHA, 0, 0},
-       {R_028430_DB_STENCILREFMASK, 0, 0},
-       {R_028434_DB_STENCILREFMASK_BF, 0, 0},
-       {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
-       {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
-       {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
-       {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
-       {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
-       {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
-       {R_0285BC_PA_CL_UCP0_X, 0, 0},
-       {R_0285C0_PA_CL_UCP0_Y, 0, 0},
-       {R_0285C4_PA_CL_UCP0_Z, 0, 0},
-       {R_0285C8_PA_CL_UCP0_W, 0, 0},
-       {R_0285CC_PA_CL_UCP1_X, 0, 0},
-       {R_0285D0_PA_CL_UCP1_Y, 0, 0},
-       {R_0285D4_PA_CL_UCP1_Z, 0, 0},
-       {R_0285D8_PA_CL_UCP1_W, 0, 0},
-       {R_0285DC_PA_CL_UCP2_X, 0, 0},
-       {R_0285E0_PA_CL_UCP2_Y, 0, 0},
-       {R_0285E4_PA_CL_UCP2_Z, 0, 0},
-       {R_0285E8_PA_CL_UCP2_W, 0, 0},
-       {R_0285EC_PA_CL_UCP3_X, 0, 0},
-       {R_0285F0_PA_CL_UCP3_Y, 0, 0},
-       {R_0285F4_PA_CL_UCP3_Z, 0, 0},
-       {R_0285F8_PA_CL_UCP3_W, 0, 0},
-       {R_0285FC_PA_CL_UCP4_X, 0, 0},
-       {R_028600_PA_CL_UCP4_Y, 0, 0},
-       {R_028604_PA_CL_UCP4_Z, 0, 0},
-       {R_028608_PA_CL_UCP4_W, 0, 0},
-       {R_02860C_PA_CL_UCP5_X, 0, 0},
-       {R_028610_PA_CL_UCP5_Y, 0, 0},
-       {R_028614_PA_CL_UCP5_Z, 0, 0},
-       {R_028618_PA_CL_UCP5_W, 0, 0},
-       {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
        {R_028620_SPI_VS_OUT_ID_1, 0, 0},
        {R_028624_SPI_VS_OUT_ID_2, 0, 0},
@@ -404,42 +367,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
        {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
-       {R_028414_CB_BLEND_RED, 0, 0},
-       {R_028418_CB_BLEND_GREEN, 0, 0},
-       {R_02841C_CB_BLEND_BLUE, 0, 0},
-       {R_028420_CB_BLEND_ALPHA, 0, 0},
-       {R_028430_DB_STENCILREFMASK, 0, 0},
-       {R_028434_DB_STENCILREFMASK_BF, 0, 0},
-       {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
-       {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
-       {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
-       {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
-       {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
-       {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
-       {R_0285BC_PA_CL_UCP0_X, 0, 0},
-       {R_0285C0_PA_CL_UCP0_Y, 0, 0},
-       {R_0285C4_PA_CL_UCP0_Z, 0, 0},
-       {R_0285C8_PA_CL_UCP0_W, 0, 0},
-       {R_0285CC_PA_CL_UCP1_X, 0, 0},
-       {R_0285D0_PA_CL_UCP1_Y, 0, 0},
-       {R_0285D4_PA_CL_UCP1_Z, 0, 0},
-       {R_0285D8_PA_CL_UCP1_W, 0, 0},
-       {R_0285DC_PA_CL_UCP2_X, 0, 0},
-       {R_0285E0_PA_CL_UCP2_Y, 0, 0},
-       {R_0285E4_PA_CL_UCP2_Z, 0, 0},
-       {R_0285E8_PA_CL_UCP2_W, 0, 0},
-       {R_0285EC_PA_CL_UCP3_X, 0, 0},
-       {R_0285F0_PA_CL_UCP3_Y, 0, 0},
-       {R_0285F4_PA_CL_UCP3_Z, 0, 0},
-       {R_0285F8_PA_CL_UCP3_W, 0, 0},
-       {R_0285FC_PA_CL_UCP4_X, 0, 0},
-       {R_028600_PA_CL_UCP4_Y, 0, 0},
-       {R_028604_PA_CL_UCP4_Z, 0, 0},
-       {R_028608_PA_CL_UCP4_W, 0, 0},
-       {R_02860C_PA_CL_UCP5_X, 0, 0},
-       {R_028610_PA_CL_UCP5_Y, 0, 0},
-       {R_028614_PA_CL_UCP5_Z, 0, 0},
-       {R_028618_PA_CL_UCP5_W, 0, 0},
        {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
        {R_028620_SPI_VS_OUT_ID_1, 0, 0},
        {R_028624_SPI_VS_OUT_ID_2, 0, 0},