* Authors:
* Jerome Glisse
*/
-#include "r600.h"
-#include "r600_hw_context_priv.h"
#include "r600_pipe.h"
#include "evergreend.h"
#include "util/u_memory.h"
-#include <errno.h>
-
-static const struct r600_reg evergreen_config_reg_list[] = {
- {R_008958_VGT_PRIMITIVE_TYPE, 0},
-};
-
-
-static const struct r600_reg cayman_config_reg_list[] = {
- {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
- {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
- {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
-};
-
-static const struct r600_reg evergreen_ctl_const_list[] = {
- {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
-};
-
-static const struct r600_reg evergreen_context_reg_list[] = {
- {R_028000_DB_RENDER_CONTROL, 0, 0},
- {R_028008_DB_DEPTH_VIEW, 0, 0},
- {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0},
- {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028044_DB_STENCIL_INFO, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028058_DB_DEPTH_SIZE, 0, 0},
- {R_02805C_DB_DEPTH_SLICE, 0, 0},
- {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
- {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
- {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0},
- {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0},
- {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0},
- {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0},
- {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0},
- {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0},
- {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0},
- {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0},
- {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0},
- {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
- {R_028238_CB_TARGET_MASK, 0, 0},
- {R_02823C_CB_SHADER_MASK, 0, 0},
- {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0},
- {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0},
- {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
- {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
- {R_028350_SX_MISC, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028408_VGT_INDX_OFFSET, 0, 0},
- {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
- {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
- {R_028414_CB_BLEND_RED, 0, 0},
- {R_028418_CB_BLEND_GREEN, 0, 0},
- {R_02841C_CB_BLEND_BLUE, 0, 0},
- {R_028420_CB_BLEND_ALPHA, 0, 0},
- {R_028430_DB_STENCILREFMASK, 0, 0},
- {R_028434_DB_STENCILREFMASK_BF, 0, 0},
- {R_028438_SX_ALPHA_REF, 0, 0},
- {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
- {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
- {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
- {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
- {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
- {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
- {R_0285BC_PA_CL_UCP0_X, 0, 0},
- {R_0285C0_PA_CL_UCP0_Y, 0, 0},
- {R_0285C4_PA_CL_UCP0_Z, 0, 0},
- {R_0285C8_PA_CL_UCP0_W, 0, 0},
- {R_0285CC_PA_CL_UCP1_X, 0, 0},
- {R_0285D0_PA_CL_UCP1_Y, 0, 0},
- {R_0285D4_PA_CL_UCP1_Z, 0, 0},
- {R_0285D8_PA_CL_UCP1_W, 0, 0},
- {R_0285DC_PA_CL_UCP2_X, 0, 0},
- {R_0285E0_PA_CL_UCP2_Y, 0, 0},
- {R_0285E4_PA_CL_UCP2_Z, 0, 0},
- {R_0285E8_PA_CL_UCP2_W, 0, 0},
- {R_0285EC_PA_CL_UCP3_X, 0, 0},
- {R_0285F0_PA_CL_UCP3_Y, 0, 0},
- {R_0285F4_PA_CL_UCP3_Z, 0, 0},
- {R_0285F8_PA_CL_UCP3_W, 0, 0},
- {R_0285FC_PA_CL_UCP4_X, 0, 0},
- {R_028600_PA_CL_UCP4_Y, 0, 0},
- {R_028604_PA_CL_UCP4_Z, 0, 0},
- {R_028608_PA_CL_UCP4_W, 0, 0},
- {R_02860C_PA_CL_UCP5_X, 0, 0},
- {R_028610_PA_CL_UCP5_Y, 0, 0},
- {R_028614_PA_CL_UCP5_Z, 0, 0},
- {R_028618_PA_CL_UCP5_W, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
- {R_028620_SPI_VS_OUT_ID_1, 0, 0},
- {R_028624_SPI_VS_OUT_ID_2, 0, 0},
- {R_028628_SPI_VS_OUT_ID_3, 0, 0},
- {R_02862C_SPI_VS_OUT_ID_4, 0, 0},
- {R_028630_SPI_VS_OUT_ID_5, 0, 0},
- {R_028634_SPI_VS_OUT_ID_6, 0, 0},
- {R_028638_SPI_VS_OUT_ID_7, 0, 0},
- {R_02863C_SPI_VS_OUT_ID_8, 0, 0},
- {R_028640_SPI_VS_OUT_ID_9, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
- {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
- {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
- {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
- {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
- {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
- {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
- {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
- {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
- {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
- {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
- {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
- {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
- {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
- {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
- {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
- {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
- {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
- {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
- {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
- {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
- {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
- {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
- {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
- {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
- {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
- {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
- {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
- {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
- {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
- {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
- {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
- {R_0286C8_SPI_THREAD_GROUPING, 0, 0},
- {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
- {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
- {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
- {R_0286D8_SPI_INPUT_Z, 0, 0},
- {R_0286E0_SPI_BARYC_CNTL, 0, 0},
- {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
- {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
- {R_028780_CB_BLEND0_CONTROL, 0, 0},
- {R_028784_CB_BLEND1_CONTROL, 0, 0},
- {R_028788_CB_BLEND2_CONTROL, 0, 0},
- {R_02878C_CB_BLEND3_CONTROL, 0, 0},
- {R_028790_CB_BLEND4_CONTROL, 0, 0},
- {R_028794_CB_BLEND5_CONTROL, 0, 0},
- {R_028798_CB_BLEND6_CONTROL, 0, 0},
- {R_02879C_CB_BLEND7_CONTROL, 0, 0},
- {R_028800_DB_DEPTH_CONTROL, 0, 0},
- {R_02880C_DB_SHADER_CONTROL, 0, 0},
- {R_028808_CB_COLOR_CONTROL, 0, 0},
- {R_028810_PA_CL_CLIP_CNTL, 0, 0},
- {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
- {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
- {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
- {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
- {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
- {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
- {R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
- {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
- {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0},
- {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0},
- {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0},
- {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0},
- {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0},
- {R_028A00_PA_SU_POINT_SIZE, 0, 0},
- {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
- {R_028A08_PA_SU_LINE_CNTL, 0, 0},
- {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
- {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
- {R_028ABC_DB_HTILE_SURFACE, 0, 0},
- {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
- {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
- {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
- {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
- {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
- {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
- {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
- {R_028C08_PA_SU_VTX_CNTL, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0},
- {R_028C64_CB_COLOR0_PITCH, 0, 0},
- {R_028C68_CB_COLOR0_SLICE, 0, 0},
- {R_028C6C_CB_COLOR0_VIEW, 0, 0},
- {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
- {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028C78_CB_COLOR0_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0},
- {R_028CA0_CB_COLOR1_PITCH, 0, 0},
- {R_028CA4_CB_COLOR1_SLICE, 0, 0},
- {R_028CA8_CB_COLOR1_VIEW, 0, 0},
- {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
- {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028CB4_CB_COLOR1_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0},
- {R_028CDC_CB_COLOR2_PITCH, 0, 0},
- {R_028CE0_CB_COLOR2_SLICE, 0, 0},
- {R_028CE4_CB_COLOR2_VIEW, 0, 0},
- {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
- {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028CF0_CB_COLOR2_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0},
- {R_028D18_CB_COLOR3_PITCH, 0, 0},
- {R_028D1C_CB_COLOR3_SLICE, 0, 0},
- {R_028D20_CB_COLOR3_VIEW, 0, 0},
- {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
- {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028D2C_CB_COLOR3_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0},
- {R_028D54_CB_COLOR4_PITCH, 0, 0},
- {R_028D58_CB_COLOR4_SLICE, 0, 0},
- {R_028D5C_CB_COLOR4_VIEW, 0, 0},
- {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
- {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028D68_CB_COLOR4_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0},
- {R_028D90_CB_COLOR5_PITCH, 0, 0},
- {R_028D94_CB_COLOR5_SLICE, 0, 0},
- {R_028D98_CB_COLOR5_VIEW, 0, 0},
- {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
- {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028DA4_CB_COLOR5_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0},
- {R_028DCC_CB_COLOR6_PITCH, 0, 0},
- {R_028DD0_CB_COLOR6_SLICE, 0, 0},
- {R_028DD4_CB_COLOR6_VIEW, 0, 0},
- {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
- {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028DE0_CB_COLOR6_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0},
- {R_028E08_CB_COLOR7_PITCH, 0, 0},
- {R_028E0C_CB_COLOR7_SLICE, 0, 0},
- {R_028E10_CB_COLOR7_VIEW, 0, 0},
- {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
- {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028E1C_CB_COLOR7_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0},
- {R_028E44_CB_COLOR8_PITCH, 0, 0},
- {R_028E48_CB_COLOR8_SLICE, 0, 0},
- {R_028E4C_CB_COLOR8_VIEW, 0, 0},
- {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0},
- {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028E58_CB_COLOR8_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0},
- {R_028E60_CB_COLOR9_PITCH, 0, 0},
- {R_028E64_CB_COLOR9_SLICE, 0, 0},
- {R_028E68_CB_COLOR9_VIEW, 0, 0},
- {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0},
- {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028E74_CB_COLOR9_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0},
- {R_028E7C_CB_COLOR10_PITCH, 0, 0},
- {R_028E80_CB_COLOR10_SLICE, 0, 0},
- {R_028E84_CB_COLOR10_VIEW, 0, 0},
- {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0},
- {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028E90_CB_COLOR10_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0},
- {R_028E98_CB_COLOR11_PITCH, 0, 0},
- {R_028E9C_CB_COLOR11_SLICE, 0, 0},
- {R_028EA0_CB_COLOR11_VIEW, 0, 0},
- {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0},
- {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028EAC_CB_COLOR11_DIM, 0, 0},
-};
-
-static const struct r600_reg cayman_context_reg_list[] = {
- {R_028000_DB_RENDER_CONTROL, 0, 0},
- {R_028008_DB_DEPTH_VIEW, 0, 0},
- {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0},
- {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028044_DB_STENCIL_INFO, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028058_DB_DEPTH_SIZE, 0, 0},
- {R_02805C_DB_DEPTH_SLICE, 0, 0},
- {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
- {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
- {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0},
- {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0},
- {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0},
- {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0},
- {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0},
- {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0},
- {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0},
- {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0},
- {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0},
- {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
- {R_028238_CB_TARGET_MASK, 0, 0},
- {R_02823C_CB_SHADER_MASK, 0, 0},
- {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0},
- {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0},
- {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
- {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
- {R_028350_SX_MISC, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028408_VGT_INDX_OFFSET, 0, 0},
- {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
- {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
- {R_028414_CB_BLEND_RED, 0, 0},
- {R_028418_CB_BLEND_GREEN, 0, 0},
- {R_02841C_CB_BLEND_BLUE, 0, 0},
- {R_028420_CB_BLEND_ALPHA, 0, 0},
- {R_028430_DB_STENCILREFMASK, 0, 0},
- {R_028434_DB_STENCILREFMASK_BF, 0, 0},
- {R_028438_SX_ALPHA_REF, 0, 0},
- {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
- {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
- {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
- {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
- {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
- {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
- {R_0285BC_PA_CL_UCP0_X, 0, 0},
- {R_0285C0_PA_CL_UCP0_Y, 0, 0},
- {R_0285C4_PA_CL_UCP0_Z, 0, 0},
- {R_0285C8_PA_CL_UCP0_W, 0, 0},
- {R_0285CC_PA_CL_UCP1_X, 0, 0},
- {R_0285D0_PA_CL_UCP1_Y, 0, 0},
- {R_0285D4_PA_CL_UCP1_Z, 0, 0},
- {R_0285D8_PA_CL_UCP1_W, 0, 0},
- {R_0285DC_PA_CL_UCP2_X, 0, 0},
- {R_0285E0_PA_CL_UCP2_Y, 0, 0},
- {R_0285E4_PA_CL_UCP2_Z, 0, 0},
- {R_0285E8_PA_CL_UCP2_W, 0, 0},
- {R_0285EC_PA_CL_UCP3_X, 0, 0},
- {R_0285F0_PA_CL_UCP3_Y, 0, 0},
- {R_0285F4_PA_CL_UCP3_Z, 0, 0},
- {R_0285F8_PA_CL_UCP3_W, 0, 0},
- {R_0285FC_PA_CL_UCP4_X, 0, 0},
- {R_028600_PA_CL_UCP4_Y, 0, 0},
- {R_028604_PA_CL_UCP4_Z, 0, 0},
- {R_028608_PA_CL_UCP4_W, 0, 0},
- {R_02860C_PA_CL_UCP5_X, 0, 0},
- {R_028610_PA_CL_UCP5_Y, 0, 0},
- {R_028614_PA_CL_UCP5_Z, 0, 0},
- {R_028618_PA_CL_UCP5_W, 0, 0},
- {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
- {R_028620_SPI_VS_OUT_ID_1, 0, 0},
- {R_028624_SPI_VS_OUT_ID_2, 0, 0},
- {R_028628_SPI_VS_OUT_ID_3, 0, 0},
- {R_02862C_SPI_VS_OUT_ID_4, 0, 0},
- {R_028630_SPI_VS_OUT_ID_5, 0, 0},
- {R_028634_SPI_VS_OUT_ID_6, 0, 0},
- {R_028638_SPI_VS_OUT_ID_7, 0, 0},
- {R_02863C_SPI_VS_OUT_ID_8, 0, 0},
- {R_028640_SPI_VS_OUT_ID_9, 0, 0},
- {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
- {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
- {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
- {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
- {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
- {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
- {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
- {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
- {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
- {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
- {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
- {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
- {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
- {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
- {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
- {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
- {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
- {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
- {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
- {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
- {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
- {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
- {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
- {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
- {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
- {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
- {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
- {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
- {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
- {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
- {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
- {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
- {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
- {R_0286C8_SPI_THREAD_GROUPING, 0, 0},
- {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
- {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
- {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
- {R_0286D8_SPI_INPUT_Z, 0, 0},
- {R_0286E0_SPI_BARYC_CNTL, 0, 0},
- {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
- {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
- {R_028780_CB_BLEND0_CONTROL, 0, 0},
- {R_028784_CB_BLEND1_CONTROL, 0, 0},
- {R_028788_CB_BLEND2_CONTROL, 0, 0},
- {R_02878C_CB_BLEND3_CONTROL, 0, 0},
- {R_028790_CB_BLEND4_CONTROL, 0, 0},
- {R_028794_CB_BLEND5_CONTROL, 0, 0},
- {R_028798_CB_BLEND6_CONTROL, 0, 0},
- {R_02879C_CB_BLEND7_CONTROL, 0, 0},
- {R_028800_DB_DEPTH_CONTROL, 0, 0},
- {R_028808_CB_COLOR_CONTROL, 0, 0},
- {R_02880C_DB_SHADER_CONTROL, 0, 0},
- {R_028810_PA_CL_CLIP_CNTL, 0, 0},
- {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
- {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
- {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0},
- {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
- {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
- {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
- {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
- {R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
- {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
- {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0},
- {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0},
- {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0},
- {R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0},
- {R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0},
- {R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0},
- {R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0},
- {R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0},
- {R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0},
- {R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0},
- {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0},
- {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0},
- {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0},
- {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0},
- {R_028A00_PA_SU_POINT_SIZE, 0, 0},
- {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
- {R_028A08_PA_SU_LINE_CNTL, 0, 0},
- {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
- {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
- {R_028ABC_DB_HTILE_SURFACE, 0, 0},
- {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
- {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
- {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
- {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
- {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
- {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
- {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
- {CM_R_028BE4_PA_SU_VTX_CNTL, 0, 0},
- {CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0, 0},
- {CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0, 0},
- {CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0, 0},
- {CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0, 0},
- {CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0, 0},
- {CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, 0, 0},
- {CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0, 0},
- {CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0, 0},
- {CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0, 0},
- {CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, 0, 0},
- {CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0, 0},
- {CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0, 0},
- {CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0, 0},
- {CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, 0, 0},
- {CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, 0, 0},
- {CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0},
- {R_028C64_CB_COLOR0_PITCH, 0, 0},
- {R_028C68_CB_COLOR0_SLICE, 0, 0},
- {R_028C6C_CB_COLOR0_VIEW, 0, 0},
- {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
- {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028C78_CB_COLOR0_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0},
- {R_028CA0_CB_COLOR1_PITCH, 0, 0},
- {R_028CA4_CB_COLOR1_SLICE, 0, 0},
- {R_028CA8_CB_COLOR1_VIEW, 0, 0},
- {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
- {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028CB4_CB_COLOR1_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0},
- {R_028CDC_CB_COLOR2_PITCH, 0, 0},
- {R_028CE0_CB_COLOR2_SLICE, 0, 0},
- {R_028CE4_CB_COLOR2_VIEW, 0, 0},
- {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
- {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028CF0_CB_COLOR2_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0},
- {R_028D18_CB_COLOR3_PITCH, 0, 0},
- {R_028D1C_CB_COLOR3_SLICE, 0, 0},
- {R_028D20_CB_COLOR3_VIEW, 0, 0},
- {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
- {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028D2C_CB_COLOR3_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0},
- {R_028D54_CB_COLOR4_PITCH, 0, 0},
- {R_028D58_CB_COLOR4_SLICE, 0, 0},
- {R_028D5C_CB_COLOR4_VIEW, 0, 0},
- {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
- {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028D68_CB_COLOR4_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0},
- {R_028D90_CB_COLOR5_PITCH, 0, 0},
- {R_028D94_CB_COLOR5_SLICE, 0, 0},
- {R_028D98_CB_COLOR5_VIEW, 0, 0},
- {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
- {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028DA4_CB_COLOR5_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0},
- {R_028DCC_CB_COLOR6_PITCH, 0, 0},
- {R_028DD0_CB_COLOR6_SLICE, 0, 0},
- {R_028DD4_CB_COLOR6_VIEW, 0, 0},
- {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
- {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028DE0_CB_COLOR6_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0},
- {R_028E08_CB_COLOR7_PITCH, 0, 0},
- {R_028E0C_CB_COLOR7_SLICE, 0, 0},
- {R_028E10_CB_COLOR7_VIEW, 0, 0},
- {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
- {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028E1C_CB_COLOR7_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0},
- {R_028E44_CB_COLOR8_PITCH, 0, 0},
- {R_028E48_CB_COLOR8_SLICE, 0, 0},
- {R_028E4C_CB_COLOR8_VIEW, 0, 0},
- {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0},
- {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028E58_CB_COLOR8_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0},
- {R_028E60_CB_COLOR9_PITCH, 0, 0},
- {R_028E64_CB_COLOR9_SLICE, 0, 0},
- {R_028E68_CB_COLOR9_VIEW, 0, 0},
- {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0},
- {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028E74_CB_COLOR9_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0},
- {R_028E7C_CB_COLOR10_PITCH, 0, 0},
- {R_028E80_CB_COLOR10_SLICE, 0, 0},
- {R_028E84_CB_COLOR10_VIEW, 0, 0},
- {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0},
- {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028E90_CB_COLOR10_DIM, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0},
- {R_028E98_CB_COLOR11_PITCH, 0, 0},
- {R_028E9C_CB_COLOR11_SLICE, 0, 0},
- {R_028EA0_CB_COLOR11_VIEW, 0, 0},
- {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0},
- {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0},
- {R_028EAC_CB_COLOR11_DIM, 0, 0},
-};
-
-/* SHADER RESOURCE EG/CM */
-static int evergreen_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
+#include "util/u_math.h"
+
+void evergreen_dma_copy_buffer(struct r600_context *rctx,
+ struct pipe_resource *dst,
+ struct pipe_resource *src,
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size)
{
- struct r600_reg r600_shader_resource[] = {
- {R_030000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, 0},
- {R_030004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, 0},
- {R_030008_RESOURCE0_WORD2, 0, 0},
- {R_03000C_RESOURCE0_WORD3, 0, 0},
- {R_030010_RESOURCE0_WORD4, 0, 0},
- {R_030014_RESOURCE0_WORD5, 0, 0},
- {R_030018_RESOURCE0_WORD6, 0, 0},
- {R_03001C_RESOURCE0_WORD7, 0, 0},
- };
- unsigned nreg = Elements(r600_shader_resource);
-
- return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, EVERGREEN_RESOURCE_OFFSET);
-}
-
-/* SHADER SAMPLER BORDER EG/CM */
-static int evergreen_state_sampler_border_init(struct r600_context *ctx, uint32_t offset, unsigned id)
-{
- struct r600_reg r600_shader_sampler_border[] = {
- {R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0},
- {R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0},
- {R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0},
- {R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0},
- {R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0},
- };
- unsigned nreg = Elements(r600_shader_sampler_border);
- unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
- struct r600_range *range;
- struct r600_block *block;
- int r;
-
- for (int i = 0; i < nreg; i++) {
- r600_shader_sampler_border[i].offset -= R_00A400_TD_PS_SAMPLER0_BORDER_INDEX;
- r600_shader_sampler_border[i].offset += fake_offset;
- }
- r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, 0);
- if (r) {
- return r;
+ struct radeon_winsys_cs *cs = rctx->b.dma.cs;
+ unsigned i, ncopy, csize, sub_cmd, shift;
+ struct r600_resource *rdst = (struct r600_resource*)dst;
+ struct r600_resource *rsrc = (struct r600_resource*)src;
+
+ /* Mark the buffer range of destination as valid (initialized),
+ * so that transfer_map knows it should wait for the GPU when mapping
+ * that range. */
+ util_range_add(&rdst->valid_buffer_range, dst_offset,
+ dst_offset + size);
+
+ dst_offset += rdst->gpu_address;
+ src_offset += rsrc->gpu_address;
+
+ /* see if we use dword or byte copy */
+ if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) {
+ size >>= 2;
+ sub_cmd = EG_DMA_COPY_DWORD_ALIGNED;
+ shift = 2;
+ } else {
+ sub_cmd = EG_DMA_COPY_BYTE_ALIGNED;
+ shift = 0;
}
- /* set proper offset */
- range = &ctx->range[CTX_RANGE_ID(r600_shader_sampler_border[0].offset)];
- block = range->blocks[CTX_BLOCK_ID(r600_shader_sampler_border[0].offset)];
- block->pm4[1] = (offset - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
- return 0;
-}
-
-static int evergreen_loop_const_init(struct r600_context *ctx, uint32_t offset)
-{
- unsigned nreg = 32;
- struct r600_reg r600_loop_consts[32];
- int i;
-
- for (i = 0; i < nreg; i++) {
- r600_loop_consts[i].offset = EVERGREEN_LOOP_CONST_OFFSET + ((offset + i) * 4);
- r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
- r600_loop_consts[i].sbu_flags = 0;
+ ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
+
+ r600_need_dma_space(&rctx->b, ncopy * 5);
+ for (i = 0; i < ncopy; i++) {
+ csize = size < EG_DMA_COPY_MAX_SIZE ? size : EG_DMA_COPY_MAX_SIZE;
+ /* emit reloc before writing cs so that cs is always in consistent state */
+ radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rsrc, RADEON_USAGE_READ,
+ RADEON_PRIO_SDMA_BUFFER);
+ radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE,
+ RADEON_PRIO_SDMA_BUFFER);
+ cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, csize);
+ cs->buf[cs->cdw++] = dst_offset & 0xffffffff;
+ cs->buf[cs->cdw++] = src_offset & 0xffffffff;
+ cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff;
+ cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xff;
+ dst_offset += csize << shift;
+ src_offset += csize << shift;
+ size -= csize;
}
- return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, EVERGREEN_LOOP_CONST_OFFSET);
}
-int evergreen_context_init(struct r600_context *ctx)
-{
- int r;
-
- /* add blocks */
- if (ctx->family == CHIP_CAYMAN)
- r = r600_context_add_block(ctx, cayman_config_reg_list,
- Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
- else
- r = r600_context_add_block(ctx, evergreen_config_reg_list,
- Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
- if (r)
- goto out_err;
- if (ctx->family == CHIP_CAYMAN)
- r = r600_context_add_block(ctx, cayman_context_reg_list,
- Elements(cayman_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
- else
- r = r600_context_add_block(ctx, evergreen_context_reg_list,
- Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
- if (r)
- goto out_err;
- r = r600_context_add_block(ctx, evergreen_ctl_const_list,
- Elements(evergreen_ctl_const_list), PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET);
- if (r)
- goto out_err;
-
-
- /* PS SAMPLER */
- for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
- r = r600_state_sampler_init(ctx, offset);
- if (r)
- goto out_err;
- }
- /* VS SAMPLER */
- for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
- r = r600_state_sampler_init(ctx, offset);
- if (r)
- goto out_err;
- }
- /* PS SAMPLER BORDER */
- for (int j = 0; j < 18; j++) {
- r = evergreen_state_sampler_border_init(ctx, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, j);
- if (r)
- goto out_err;
- }
- /* VS SAMPLER BORDER */
- for (int j = 0; j < 18; j++) {
- r = evergreen_state_sampler_border_init(ctx, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, j);
- if (r)
- goto out_err;
- }
+/* The max number of bytes to copy per packet. */
+#define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
- ctx->num_ps_resources = 176;
- ctx->num_vs_resources = 160;
- ctx->num_fs_resources = 16;
- r = evergreen_resource_range_init(ctx, &ctx->ps_resources, 0, 176, 0x20);
- if (r)
- goto out_err;
- r = evergreen_resource_range_init(ctx, &ctx->vs_resources, 0x1600, 160, 0x20);
- if (r)
- goto out_err;
- r = evergreen_resource_range_init(ctx, &ctx->fs_resources, 0x7C00, 16, 0x20);
- if (r)
- goto out_err;
-
- /* PS loop const */
- evergreen_loop_const_init(ctx, 0);
- /* VS loop const */
- evergreen_loop_const_init(ctx, 32);
-
- r = r600_setup_block_table(ctx);
- if (r)
- goto out_err;
-
- ctx->max_db = 8;
- return 0;
-out_err:
- r600_context_fini(ctx);
- return r;
-}
-
-static inline void evergreen_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
+ struct pipe_resource *dst, uint64_t offset,
+ unsigned size, uint32_t clear_value)
{
- struct r600_range *range;
- struct r600_block *block;
- int i;
- int dirty;
-
- range = &ctx->range[CTX_RANGE_ID(offset)];
- block = range->blocks[CTX_BLOCK_ID(offset)];
- if (state == NULL) {
- block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
- LIST_DELINIT(&block->list);
- LIST_DELINIT(&block->enable_list);
- return;
- }
- dirty = block->status & R600_BLOCK_STATUS_DIRTY;
-
- for (i = 0; i < 3; i++) {
- if (block->reg[i] != state->regs[i].value) {
- dirty |= R600_BLOCK_STATUS_DIRTY;
- block->reg[i] = state->regs[i].value;
+ struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
+
+ assert(size);
+ assert(rctx->screen->b.has_cp_dma);
+
+ /* Mark the buffer range of destination as valid (initialized),
+ * so that transfer_map knows it should wait for the GPU when mapping
+ * that range. */
+ util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
+ offset + size);
+
+ offset += r600_resource(dst)->gpu_address;
+
+ /* Flush the cache where the resource is bound. */
+ rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
+ R600_CONTEXT_INV_VERTEX_CACHE |
+ R600_CONTEXT_INV_TEX_CACHE |
+ R600_CONTEXT_FLUSH_AND_INV |
+ R600_CONTEXT_FLUSH_AND_INV_CB |
+ R600_CONTEXT_FLUSH_AND_INV_DB |
+ R600_CONTEXT_FLUSH_AND_INV_CB_META |
+ R600_CONTEXT_FLUSH_AND_INV_DB_META |
+ R600_CONTEXT_STREAMOUT_FLUSH |
+ R600_CONTEXT_WAIT_3D_IDLE;
+
+ while (size) {
+ unsigned sync = 0;
+ unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
+ unsigned reloc;
+
+ r600_need_cs_space(rctx, 10 + (rctx->b.flags ? R600_MAX_FLUSH_CS_DWORDS : 0), FALSE);
+
+ /* Flush the caches for the first copy only. */
+ if (rctx->b.flags) {
+ r600_flush_emit(rctx);
}
- }
- if (dirty)
- r600_context_dirty_block(ctx, block, dirty, 2);
-}
-
-static inline void evergreen_context_ps_partial_flush(struct r600_context *ctx)
-{
- struct radeon_winsys_cs *cs = ctx->cs;
-
- if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
- return;
- cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
- cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
-
- ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
-}
-
-static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset, unsigned id)
-{
- unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
- struct r600_range *range;
- struct r600_block *block;
- int i;
- int dirty;
-
- range = &ctx->range[CTX_RANGE_ID(fake_offset)];
- block = range->blocks[CTX_BLOCK_ID(fake_offset)];
- if (state == NULL) {
- block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
- LIST_DELINIT(&block->list);
- LIST_DELINIT(&block->enable_list);
- return;
- }
- if (state->nregs <= 3) {
- return;
- }
-
- dirty = block->status & R600_BLOCK_STATUS_DIRTY;
- if (block->reg[0] != id) {
- block->reg[0] = id;
- dirty |= R600_BLOCK_STATUS_DIRTY;
- }
-
- for (i = 1; i < 5; i++) {
- if (block->reg[i] != state->regs[i + 2].value) {
- block->reg[i] = state->regs[i + 2].value;
- dirty |= R600_BLOCK_STATUS_DIRTY;
+ /* Do the synchronization after the last copy, so that all data is written to memory. */
+ if (size == byte_count) {
+ sync = PKT3_CP_DMA_CP_SYNC;
}
- }
- /* We have to flush the shaders before we change the border color
- * registers, or previous draw commands that haven't completed yet
- * will end up using the new border color. */
- if (dirty & R600_BLOCK_STATUS_DIRTY)
- evergreen_context_ps_partial_flush(ctx);
- if (dirty)
- r600_context_dirty_block(ctx, block, dirty, 4);
-}
+ /* This must be done after r600_need_cs_space. */
+ reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
+ (struct r600_resource*)dst, RADEON_USAGE_WRITE,
+ RADEON_PRIO_CP_DMA);
-void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
-{
- unsigned offset;
-
- offset = 0x0003C000 + id * 0xc;
- evergreen_context_pipe_state_set_sampler(ctx, state, offset);
- evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, id);
-}
-
-void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
-{
- unsigned offset;
-
- offset = 0x0003C0D8 + id * 0xc;
- evergreen_context_pipe_state_set_sampler(ctx, state, offset);
- evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, id);
-}
-
-void evergreen_flush_vgt_streamout(struct r600_context *ctx)
-{
- struct radeon_winsys_cs *cs = ctx->cs;
+ radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
+ radeon_emit(cs, clear_value); /* DATA [31:0] */
+ radeon_emit(cs, sync | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
+ radeon_emit(cs, offset); /* DST_ADDR_LO [31:0] */
+ radeon_emit(cs, (offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] */
+ radeon_emit(cs, byte_count); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = 0;
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+ radeon_emit(cs, reloc);
- cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
- cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
+ size -= byte_count;
+ offset += byte_count;
+ }
- cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
- cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
- cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2; /* register */
- cs->buf[cs->cdw++] = 0;
- cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */
- cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */
- cs->buf[cs->cdw++] = 4; /* poll interval */
+ /* Invalidate the read caches. */
+ rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
+ R600_CONTEXT_INV_VERTEX_CACHE |
+ R600_CONTEXT_INV_TEX_CACHE;
}
-void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
-{
- struct radeon_winsys_cs *cs = ctx->cs;
-
- if (buffer_enable_bit) {
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(1);
-
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit);
- } else {
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(0);
- }
-}
projects / mesa.git / blobdiff