r600g: implement timestamp query and get_timestamp hook
[mesa.git] / src / gallium / drivers / r600 / evergreen_hw_context.c
index 53d45824136e218978a40a920f2dd99d73d60220..f0c4ff7a482ca2bc6d644e8fc284cc40918acfde 100644 (file)
@@ -43,7 +43,6 @@ static const struct r600_reg evergreen_ctl_const_list[] = {
 };
 
 static const struct r600_reg evergreen_context_reg_list[] = {
-       {R_028000_DB_RENDER_CONTROL, 0, 0},
        {R_028008_DB_DEPTH_VIEW, 0, 0},
        {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
@@ -74,14 +73,12 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
        {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
-       {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
        {R_028414_CB_BLEND_RED, 0, 0},
        {R_028418_CB_BLEND_GREEN, 0, 0},
        {R_02841C_CB_BLEND_BLUE, 0, 0},
        {R_028420_CB_BLEND_ALPHA, 0, 0},
        {R_028430_DB_STENCILREFMASK, 0, 0},
        {R_028434_DB_STENCILREFMASK_BF, 0, 0},
-       {R_028438_SX_ALPHA_REF, 0, 0},
        {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
        {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
        {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
@@ -195,14 +192,26 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
        {R_028ABC_DB_HTILE_SURFACE, 0, 0},
        {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
+       {R_028B70_DB_ALPHA_TO_MASK, 0, 0},
        {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
        {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
        {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
        {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
        {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
        {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
+       {R_028C00_PA_SC_LINE_CNTL, 0, 0},
+       {R_028C04_PA_SC_AA_CONFIG, 0, 0},
        {R_028C08_PA_SU_VTX_CNTL, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
+       {R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, 0, 0},
+       {R_028C20_PA_SC_AA_SAMPLE_LOCS_1, 0, 0},
+       {R_028C24_PA_SC_AA_SAMPLE_LOCS_2, 0, 0},
+       {R_028C28_PA_SC_AA_SAMPLE_LOCS_3, 0, 0},
+       {R_028C2C_PA_SC_AA_SAMPLE_LOCS_4, 0, 0},
+       {R_028C30_PA_SC_AA_SAMPLE_LOCS_5, 0, 0},
+       {R_028C34_PA_SC_AA_SAMPLE_LOCS_6, 0, 0},
+       {R_028C38_PA_SC_AA_SAMPLE_LOCS_7, 0, 0},
+       {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0},
        {R_028C64_CB_COLOR0_PITCH, 0, 0},
        {R_028C68_CB_COLOR0_SLICE, 0, 0},
@@ -301,7 +310,6 @@ static const struct r600_reg evergreen_context_reg_list[] = {
 };
 
 static const struct r600_reg cayman_context_reg_list[] = {
-       {R_028000_DB_RENDER_CONTROL, 0, 0},
        {R_028008_DB_DEPTH_VIEW, 0, 0},
        {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
@@ -332,14 +340,12 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
        {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
-       {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
        {R_028414_CB_BLEND_RED, 0, 0},
        {R_028418_CB_BLEND_GREEN, 0, 0},
        {R_02841C_CB_BLEND_BLUE, 0, 0},
        {R_028420_CB_BLEND_ALPHA, 0, 0},
        {R_028430_DB_STENCILREFMASK, 0, 0},
        {R_028434_DB_STENCILREFMASK_BF, 0, 0},
-       {R_028438_SX_ALPHA_REF, 0, 0},
        {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
        {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
        {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
@@ -460,12 +466,15 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
        {R_028ABC_DB_HTILE_SURFACE, 0, 0},
        {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
+       {R_028B70_DB_ALPHA_TO_MASK, 0, 0},
        {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
        {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
        {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
        {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
        {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
        {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
+       {CM_R_028BDC_PA_SC_LINE_CNTL, 0, 0},
+       {CM_R_028BE0_PA_SC_AA_CONFIG, 0, 0},
        {CM_R_028BE4_PA_SU_VTX_CNTL, 0, 0},
        {CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0, 0},
        {CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0, 0},
@@ -581,55 +590,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028EAC_CB_COLOR11_DIM, 0, 0},
 };
 
-/* SHADER RESOURCE EG/CM */
-static int evergreen_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
-{
-       struct r600_reg r600_shader_resource[] = {
-               {R_030000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, 0},
-               {R_030004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, 0},
-               {R_030008_RESOURCE0_WORD2, 0, 0},
-               {R_03000C_RESOURCE0_WORD3, 0, 0},
-               {R_030010_RESOURCE0_WORD4, 0, 0},
-               {R_030014_RESOURCE0_WORD5, 0, 0},
-               {R_030018_RESOURCE0_WORD6, 0, 0},
-               {R_03001C_RESOURCE0_WORD7, 0, 0},
-       };
-       unsigned nreg = Elements(r600_shader_resource);
-
-       return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, EVERGREEN_RESOURCE_OFFSET);
-}
-
-/* SHADER SAMPLER BORDER EG/CM */
-static int evergreen_state_sampler_border_init(struct r600_context *ctx, uint32_t offset, unsigned id)
-{
-       struct r600_reg r600_shader_sampler_border[] = {
-               {R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0},
-               {R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0},
-               {R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0},
-               {R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0},
-               {R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0},
-       };
-       unsigned nreg = Elements(r600_shader_sampler_border);
-       unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
-       struct r600_range *range;
-       struct r600_block *block;
-       int r;
-
-       for (int i = 0; i < nreg; i++) {
-               r600_shader_sampler_border[i].offset -= R_00A400_TD_PS_SAMPLER0_BORDER_INDEX;
-               r600_shader_sampler_border[i].offset += fake_offset;
-       }
-       r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, 0);
-       if (r) {
-               return r;
-       }
-       /* set proper offset */
-       range = &ctx->range[CTX_RANGE_ID(r600_shader_sampler_border[0].offset)];
-       block = range->blocks[CTX_BLOCK_ID(r600_shader_sampler_border[0].offset)];
-       block->pm4[1] = (offset - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
-       return 0;
-}
-
 static int evergreen_loop_const_init(struct r600_context *ctx, uint32_t offset)
 {
        unsigned nreg = 32;
@@ -670,41 +630,6 @@ int evergreen_context_init(struct r600_context *ctx)
        if (r)
                goto out_err;
 
-
-       /* PS SAMPLER */
-       for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
-               r = r600_state_sampler_init(ctx, offset);
-               if (r)
-                       goto out_err;
-       }
-       /* VS SAMPLER */
-       for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
-               r = r600_state_sampler_init(ctx, offset);
-               if (r)
-                       goto out_err;
-       }
-       /* PS SAMPLER BORDER */
-       for (int j = 0; j < 18; j++) {
-               r = evergreen_state_sampler_border_init(ctx, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, j);
-               if (r)
-                       goto out_err;
-       }
-       /* VS SAMPLER BORDER */
-       for (int j = 0; j < 18; j++) {
-               r = evergreen_state_sampler_border_init(ctx, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, j);
-               if (r)
-                       goto out_err;
-       }
-
-       ctx->num_ps_resources = 176;
-       ctx->num_vs_resources = 160;
-       r = evergreen_resource_range_init(ctx, &ctx->ps_resources, 0, 176, 0x20);
-       if (r)
-               goto out_err;
-       r = evergreen_resource_range_init(ctx, &ctx->vs_resources, 0x1600, 160, 0x20);
-       if (r)
-               goto out_err;
-
        /* PS loop const */
        evergreen_loop_const_init(ctx, 0);
        /* VS loop const */
@@ -721,66 +646,6 @@ out_err:
        return r;
 }
 
-static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset, unsigned id)
-{
-       unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
-       struct r600_range *range;
-       struct r600_block *block;
-       int i;
-       int dirty;
-
-       range = &ctx->range[CTX_RANGE_ID(fake_offset)];
-       block = range->blocks[CTX_BLOCK_ID(fake_offset)];
-       if (state == NULL) {
-               block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
-               LIST_DELINIT(&block->list);
-               LIST_DELINIT(&block->enable_list);
-               return;
-       }
-       if (state->nregs <= 3) {
-               return;
-       }
-
-       dirty = block->status & R600_BLOCK_STATUS_DIRTY;
-       if (block->reg[0] != id) {
-               block->reg[0] = id;
-               dirty |= R600_BLOCK_STATUS_DIRTY;
-       }
-
-       for (i = 1; i < 5; i++) {
-               if (block->reg[i] != state->regs[i + 2].value) {
-                       block->reg[i] = state->regs[i + 2].value;
-                       dirty |= R600_BLOCK_STATUS_DIRTY;
-               }
-       }
-
-       /* We have to flush the shaders before we change the border color
-        * registers, or previous draw commands that haven't completed yet
-        * will end up using the new border color. */
-       if (dirty & R600_BLOCK_STATUS_DIRTY)
-               r600_context_ps_partial_flush(ctx);
-       if (dirty)
-               r600_context_dirty_block(ctx, block, dirty, 4);
-}
-
-void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
-{
-       unsigned offset;
-
-       offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*id;
-       r600_context_pipe_state_set_sampler(ctx, state, offset);
-       evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, id);
-}
-
-void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
-{
-       unsigned offset;
-
-       offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*(id + 18);
-       r600_context_pipe_state_set_sampler(ctx, state, offset);
-       evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, id);
-}
-
 void evergreen_flush_vgt_streamout(struct r600_context *ctx)
 {
        struct radeon_winsys_cs *cs = ctx->cs;