* Authors:
* Jerome Glisse
*/
-#include "r600.h"
#include "r600_hw_context_priv.h"
-#include "r600_pipe.h"
#include "evergreend.h"
#include "util/u_memory.h"
-#include <errno.h>
-
-#define GROUP_FORCE_NEW_BLOCK 0
static const struct r600_reg evergreen_config_reg_list[] = {
{R_008958_VGT_PRIMITIVE_TYPE, 0},
};
static const struct r600_reg evergreen_context_reg_list[] = {
- {R_028000_DB_RENDER_CONTROL, 0, 0},
- {R_028004_DB_COUNT_CONTROL, 0, 0},
{R_028008_DB_DEPTH_VIEW, 0, 0},
- {R_02800C_DB_RENDER_OVERRIDE, 0, 0},
{R_028010_DB_RENDER_OVERRIDE2, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028028_DB_STENCIL_CLEAR, 0, 0},
- {R_02802C_DB_DEPTH_CLEAR, 0, 0},
- {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0},
- {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028044_DB_STENCIL_INFO, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028058_DB_DEPTH_SIZE, 0, 0},
{R_02805C_DB_DEPTH_SLICE, 0, 0},
- {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028200_PA_SC_WINDOW_OFFSET, 0, 0},
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
- {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0},
- {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0},
- {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0},
- {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0},
- {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0},
- {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0},
- {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0},
- {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0},
- {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0},
- {R_028230_PA_SC_EDGERULE, 0, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
- {R_028238_CB_TARGET_MASK, 0, 0},
- {R_02823C_CB_SHADER_MASK, 0, 0},
- {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0},
- {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
- {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0},
- {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0},
{R_028350_SX_MISC, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028408_VGT_INDX_OFFSET, 0, 0},
{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
{R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
{R_028414_CB_BLEND_RED, 0, 0},
{R_028418_CB_BLEND_GREEN, 0, 0},
{R_02841C_CB_BLEND_BLUE, 0, 0},
{R_028420_CB_BLEND_ALPHA, 0, 0},
{R_028430_DB_STENCILREFMASK, 0, 0},
{R_028434_DB_STENCILREFMASK_BF, 0, 0},
- {R_028438_SX_ALPHA_REF, 0, 0},
{R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
{R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
{R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
{R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
{R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
{R_0286D8_SPI_INPUT_Z, 0, 0},
- {R_0286DC_SPI_FOG_CNTL, 0, 0},
{R_0286E0_SPI_BARYC_CNTL, 0, 0},
{R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
{R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
{R_028808_CB_COLOR_CONTROL, 0, 0},
{R_028810_PA_CL_CLIP_CNTL, 0, 0},
{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
- {R_028818_PA_CL_VTE_CNTL, 0, 0},
{R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
- {R_028820_PA_CL_NANINF_CNTL, 0, 0},
{R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
{R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
- {R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0},
{R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
{R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
{R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
- {R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0},
{R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
- {R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0},
{R_0288EC_SQ_LDS_ALLOC_PS, 0, 0},
- {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0},
- {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0},
- {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0},
- {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0},
{R_028A00_PA_SU_POINT_SIZE, 0, 0},
{R_028A04_PA_SU_POINT_MINMAX, 0, 0},
{R_028A08_PA_SU_LINE_CNTL, 0, 0},
{R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
{R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
+ {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
{R_028ABC_DB_HTILE_SURFACE, 0, 0},
- {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0},
- {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0},
- {R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
{R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
{R_028B70_DB_ALPHA_TO_MASK, 0, 0},
{R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
{R_028C00_PA_SC_LINE_CNTL, 0, 0},
{R_028C04_PA_SC_AA_CONFIG, 0, 0},
{R_028C08_PA_SU_VTX_CNTL, 0, 0},
- {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0},
- {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0},
- {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0},
- {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0},
+ {GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, 0, 0},
- {R_028C3C_PA_SC_AA_MASK, 0, 0},
+ {R_028C20_PA_SC_AA_SAMPLE_LOCS_1, 0, 0},
+ {R_028C24_PA_SC_AA_SAMPLE_LOCS_2, 0, 0},
+ {R_028C28_PA_SC_AA_SAMPLE_LOCS_3, 0, 0},
+ {R_028C2C_PA_SC_AA_SAMPLE_LOCS_4, 0, 0},
+ {R_028C30_PA_SC_AA_SAMPLE_LOCS_5, 0, 0},
+ {R_028C34_PA_SC_AA_SAMPLE_LOCS_6, 0, 0},
+ {R_028C38_PA_SC_AA_SAMPLE_LOCS_7, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0},
{R_028C64_CB_COLOR0_PITCH, 0, 0},
};
static const struct r600_reg cayman_context_reg_list[] = {
- {R_028000_DB_RENDER_CONTROL, 0, 0},
- {R_028004_DB_COUNT_CONTROL, 0, 0},
{R_028008_DB_DEPTH_VIEW, 0, 0},
- {R_02800C_DB_RENDER_OVERRIDE, 0, 0},
{R_028010_DB_RENDER_OVERRIDE2, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028028_DB_STENCIL_CLEAR, 0, 0},
- {R_02802C_DB_DEPTH_CLEAR, 0, 0},
- {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0},
- {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028044_DB_STENCIL_INFO, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028058_DB_DEPTH_SIZE, 0, 0},
{R_02805C_DB_DEPTH_SLICE, 0, 0},
- {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028200_PA_SC_WINDOW_OFFSET, 0, 0},
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
- {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0},
- {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0},
- {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0},
- {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0},
- {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0},
- {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0},
- {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0},
- {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0},
- {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0},
- {R_028230_PA_SC_EDGERULE, 0, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
- {R_028238_CB_TARGET_MASK, 0, 0},
- {R_02823C_CB_SHADER_MASK, 0, 0},
- {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0},
- {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
- {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0},
- {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0},
{R_028350_SX_MISC, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028408_VGT_INDX_OFFSET, 0, 0},
{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
{R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
{R_028414_CB_BLEND_RED, 0, 0},
{R_028418_CB_BLEND_GREEN, 0, 0},
{R_02841C_CB_BLEND_BLUE, 0, 0},
{R_028420_CB_BLEND_ALPHA, 0, 0},
{R_028430_DB_STENCILREFMASK, 0, 0},
{R_028434_DB_STENCILREFMASK_BF, 0, 0},
- {R_028438_SX_ALPHA_REF, 0, 0},
{R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
{R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
{R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
{R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
{R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
{R_0286D8_SPI_INPUT_Z, 0, 0},
- {R_0286DC_SPI_FOG_CNTL, 0, 0},
{R_0286E0_SPI_BARYC_CNTL, 0, 0},
{R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
{R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
{R_02880C_DB_SHADER_CONTROL, 0, 0},
{R_028810_PA_CL_CLIP_CNTL, 0, 0},
{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
- {R_028818_PA_CL_VTE_CNTL, 0, 0},
{R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
- {R_028820_PA_CL_NANINF_CNTL, 0, 0},
{R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0},
{R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
{R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
- {R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0},
{R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
{R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
{R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
- {R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0},
{R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
- {R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0},
{R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0},
{R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0},
{R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0},
{R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0},
{R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0},
{R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0},
- {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0},
- {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0},
- {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0},
- {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0},
{R_028A00_PA_SU_POINT_SIZE, 0, 0},
{R_028A04_PA_SU_POINT_MINMAX, 0, 0},
{R_028A08_PA_SU_LINE_CNTL, 0, 0},
{R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
{R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
+ {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
{R_028ABC_DB_HTILE_SURFACE, 0, 0},
- {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0},
- {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0},
- {R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
{R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
{R_028B70_DB_ALPHA_TO_MASK, 0, 0},
{R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
{CM_R_028BDC_PA_SC_LINE_CNTL, 0, 0},
{CM_R_028BE0_PA_SC_AA_CONFIG, 0, 0},
{CM_R_028BE4_PA_SU_VTX_CNTL, 0, 0},
- {CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0, 0},
- {CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0, 0},
- {CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0},
- {CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0, 0},
{CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0, 0},
{CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0, 0},
{CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0, 0},
{CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, 0, 0},
{CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, 0, 0},
{CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, 0, 0},
- {CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0, 0},
- {CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0},
{R_028C64_CB_COLOR0_PITCH, 0, 0},
{R_028EAC_CB_COLOR11_DIM, 0, 0},
};
-/* SHADER RESOURCE R600/R700 */
-static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
-{
- struct r600_reg r600_shader_resource[] = {
- {R_030000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, 0},
- {R_030004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, 0},
- {R_030008_RESOURCE0_WORD2, 0, 0},
- {R_03000C_RESOURCE0_WORD3, 0, 0},
- {R_030010_RESOURCE0_WORD4, 0, 0},
- {R_030014_RESOURCE0_WORD5, 0, 0},
- {R_030018_RESOURCE0_WORD6, 0, 0},
- {R_03001C_RESOURCE0_WORD7, 0, 0},
- };
- unsigned nreg = Elements(r600_shader_resource);
-
- return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, EVERGREEN_RESOURCE_OFFSET);
-}
-
-/* SHADER SAMPLER R600/R700 */
-static int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset)
-{
- struct r600_reg r600_shader_sampler[] = {
- {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0},
- {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0},
- {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0},
- };
- unsigned nreg = Elements(r600_shader_sampler);
-
- for (int i = 0; i < nreg; i++) {
- r600_shader_sampler[i].offset += offset;
- }
- return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET);
-}
-
-/* SHADER SAMPLER BORDER EG/CM */
-static int evergreen_state_sampler_border_init(struct r600_context *ctx, uint32_t offset, unsigned id)
-{
- struct r600_reg r600_shader_sampler_border[] = {
- {R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0},
- {R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0},
- {R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0},
- {R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0},
- {R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0},
- };
- unsigned nreg = Elements(r600_shader_sampler_border);
- unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
- struct r600_range *range;
- struct r600_block *block;
- int r;
-
- for (int i = 0; i < nreg; i++) {
- r600_shader_sampler_border[i].offset -= R_00A400_TD_PS_SAMPLER0_BORDER_INDEX;
- r600_shader_sampler_border[i].offset += fake_offset;
- }
- r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, 0);
- if (r) {
- return r;
- }
- /* set proper offset */
- range = &ctx->range[CTX_RANGE_ID(r600_shader_sampler_border[0].offset)];
- block = range->blocks[CTX_BLOCK_ID(r600_shader_sampler_border[0].offset)];
- block->pm4[1] = (offset - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
- return 0;
-}
-
static int evergreen_loop_const_init(struct r600_context *ctx, uint32_t offset)
{
unsigned nreg = 32;
{
int r;
- LIST_INITHEAD(&ctx->active_query_list);
-
- /* init dirty list */
- LIST_INITHEAD(&ctx->dirty);
- LIST_INITHEAD(&ctx->resource_dirty);
- LIST_INITHEAD(&ctx->enable_list);
-
- ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
- if (!ctx->range) {
- r = -ENOMEM;
- goto out_err;
- }
-
/* add blocks */
- if (ctx->family == CHIP_CAYMAN)
+ if (ctx->family >= CHIP_CAYMAN)
r = r600_context_add_block(ctx, cayman_config_reg_list,
Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
else
Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
if (r)
goto out_err;
- if (ctx->family == CHIP_CAYMAN)
+ if (ctx->family >= CHIP_CAYMAN)
r = r600_context_add_block(ctx, cayman_context_reg_list,
Elements(cayman_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
else
if (r)
goto out_err;
-
- /* PS SAMPLER */
- for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
- r = r600_state_sampler_init(ctx, offset);
- if (r)
- goto out_err;
- }
- /* VS SAMPLER */
- for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
- r = r600_state_sampler_init(ctx, offset);
- if (r)
- goto out_err;
- }
- /* PS SAMPLER BORDER */
- for (int j = 0; j < 18; j++) {
- r = evergreen_state_sampler_border_init(ctx, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, j);
- if (r)
- goto out_err;
- }
- /* VS SAMPLER BORDER */
- for (int j = 0; j < 18; j++) {
- r = evergreen_state_sampler_border_init(ctx, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, j);
- if (r)
- goto out_err;
- }
-
- ctx->num_ps_resources = 176;
- ctx->num_vs_resources = 160;
- ctx->num_fs_resources = 16;
- r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 176, 0x20);
- if (r)
- goto out_err;
- r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1600, 160, 0x20);
- if (r)
- goto out_err;
- r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x7C00, 16, 0x20);
- if (r)
- goto out_err;
-
/* PS loop const */
evergreen_loop_const_init(ctx, 0);
/* VS loop const */
if (r)
goto out_err;
- ctx->cs = ctx->ws->cs_create(ctx->ws);
- r600_emit_atom(ctx, &ctx->atom_start_cs.atom);
-
ctx->max_db = 8;
return 0;
out_err:
return r;
}
-void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
-{
- struct r600_block *block = ctx->ps_resources.blocks[rid];
-
- r600_context_pipe_state_set_resource(ctx, state, block);
-}
-
-void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
-{
- struct r600_block *block = ctx->vs_resources.blocks[rid];
-
- r600_context_pipe_state_set_resource(ctx, state, block);
-}
-
-void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
-{
- struct r600_block *block = ctx->fs_resources.blocks[rid];
-
- r600_context_pipe_state_set_resource(ctx, state, block);
-}
-
-static inline void evergreen_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
-{
- struct r600_range *range;
- struct r600_block *block;
- int i;
- int dirty;
-
- range = &ctx->range[CTX_RANGE_ID(offset)];
- block = range->blocks[CTX_BLOCK_ID(offset)];
- if (state == NULL) {
- block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
- LIST_DELINIT(&block->list);
- LIST_DELINIT(&block->enable_list);
- return;
- }
- dirty = block->status & R600_BLOCK_STATUS_DIRTY;
-
- for (i = 0; i < 3; i++) {
- if (block->reg[i] != state->regs[i].value) {
- dirty |= R600_BLOCK_STATUS_DIRTY;
- block->reg[i] = state->regs[i].value;
- }
- }
- if (dirty)
- r600_context_dirty_block(ctx, block, dirty, 2);
-}
-
-static inline void evergreen_context_ps_partial_flush(struct r600_context *ctx)
-{
- struct radeon_winsys_cs *cs = ctx->cs;
-
- if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
- return;
-
- cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
- cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
-
- ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
-}
-
-static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset, unsigned id)
-{
- unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
- struct r600_range *range;
- struct r600_block *block;
- int i;
- int dirty;
-
- range = &ctx->range[CTX_RANGE_ID(fake_offset)];
- block = range->blocks[CTX_BLOCK_ID(fake_offset)];
- if (state == NULL) {
- block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
- LIST_DELINIT(&block->list);
- LIST_DELINIT(&block->enable_list);
- return;
- }
- if (state->nregs <= 3) {
- return;
- }
-
- dirty = block->status & R600_BLOCK_STATUS_DIRTY;
- if (block->reg[0] != id) {
- block->reg[0] = id;
- dirty |= R600_BLOCK_STATUS_DIRTY;
- }
-
- for (i = 1; i < 5; i++) {
- if (block->reg[i] != state->regs[i + 2].value) {
- block->reg[i] = state->regs[i + 2].value;
- dirty |= R600_BLOCK_STATUS_DIRTY;
- }
- }
-
- /* We have to flush the shaders before we change the border color
- * registers, or previous draw commands that haven't completed yet
- * will end up using the new border color. */
- if (dirty & R600_BLOCK_STATUS_DIRTY)
- evergreen_context_ps_partial_flush(ctx);
- if (dirty)
- r600_context_dirty_block(ctx, block, dirty, 4);
-}
-
-void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
-{
- unsigned offset;
-
- offset = 0x0003C000 + id * 0xc;
- evergreen_context_pipe_state_set_sampler(ctx, state, offset);
- evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, id);
-}
-
-void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
-{
- unsigned offset;
-
- offset = 0x0003C0D8 + id * 0xc;
- evergreen_context_pipe_state_set_sampler(ctx, state, offset);
- evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, id);
-}
-
-/* XXX make a proper state object (atom or pipe_state) out of this */
-void evergreen_context_draw_prepare(struct r600_context *ctx)
-{
- struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)ctx->states[R600_PIPE_STATE_DSA];
- struct radeon_winsys_cs *cs = ctx->cs;
-
- /* queries need some special values
- * (this is non-zero if any query is active) */
- if (ctx->num_cs_dw_queries_suspend) {
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_028004_DB_COUNT_CONTROL - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = S_028004_PERFECT_ZPASS_COUNTS(1);
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_02800C_DB_RENDER_OVERRIDE - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = dsa->db_render_override | S_02800C_NOOP_CULL_DISABLE(1);
- }
-}
-
void evergreen_flush_vgt_streamout(struct r600_context *ctx)
{
struct radeon_winsys_cs *cs = ctx->cs;
projects / mesa.git / blobdiff