#include "util/u_framebuffer.h"
#include "util/u_dual_blend.h"
#include "evergreen_compute.h"
+#include "util/u_math.h"
+
+static INLINE unsigned evergreen_array_mode(unsigned mode)
+{
+ switch (mode) {
+ case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
+ break;
+ case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
+ break;
+ case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
+ default:
+ case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL;
+ }
+}
static uint32_t eg_num_banks(uint32_t nbanks)
{
case PIPE_TEXTURE_3D:
return V_030000_SQ_TEX_DIM_3D;
case PIPE_TEXTURE_CUBE:
+ case PIPE_TEXTURE_CUBE_ARRAY:
return V_030000_SQ_TEX_DIM_CUBEMAP;
}
}
return V_028040_Z_16;
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ case PIPE_FORMAT_X8Z24_UNORM:
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
return V_028040_Z_24;
case PIPE_FORMAT_Z32_FLOAT:
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
case PIPE_FORMAT_L32A32_UINT:
case PIPE_FORMAT_L32A32_SINT:
case PIPE_FORMAT_L32A32_FLOAT:
+ case PIPE_FORMAT_R8A8_UNORM:
+ case PIPE_FORMAT_R8A8_SNORM:
+ case PIPE_FORMAT_R8A8_UINT:
+ case PIPE_FORMAT_R8A8_SINT:
+ case PIPE_FORMAT_R16A16_UNORM:
+ case PIPE_FORMAT_R16A16_SNORM:
+ case PIPE_FORMAT_R16A16_UINT:
+ case PIPE_FORMAT_R16A16_SINT:
+ case PIPE_FORMAT_R16A16_FLOAT:
+ case PIPE_FORMAT_R32A32_UINT:
+ case PIPE_FORMAT_R32A32_SINT:
+ case PIPE_FORMAT_R32A32_FLOAT:
return V_028C70_SWAP_ALT;
case PIPE_FORMAT_R8G8_UNORM:
case PIPE_FORMAT_R8G8_SNORM:
case PIPE_FORMAT_R8G8B8A8_SINT:
case PIPE_FORMAT_R8G8B8A8_UINT:
case PIPE_FORMAT_R8G8B8X8_UNORM:
+ case PIPE_FORMAT_R8G8B8X8_SNORM:
+ case PIPE_FORMAT_R8G8B8X8_SRGB:
+ case PIPE_FORMAT_R8G8B8X8_UINT:
+ case PIPE_FORMAT_R8G8B8X8_SINT:
return V_028C70_SWAP_STD;
case PIPE_FORMAT_A8B8G8R8_UNORM:
case PIPE_FORMAT_X8Z24_UNORM:
case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- return V_028C70_SWAP_STD;
+ return V_028C70_SWAP_STD_REV;
case PIPE_FORMAT_R10G10B10A2_UNORM:
case PIPE_FORMAT_R10G10B10X2_SNORM:
case PIPE_FORMAT_B10G10R10A2_UNORM:
case PIPE_FORMAT_B10G10R10A2_UINT:
+ case PIPE_FORMAT_B10G10R10X2_UNORM:
return V_028C70_SWAP_ALT;
case PIPE_FORMAT_R11G11B10_FLOAT:
case PIPE_FORMAT_R16G16B16A16_UINT:
case PIPE_FORMAT_R16G16B16A16_SINT:
case PIPE_FORMAT_R16G16B16A16_FLOAT:
+ case PIPE_FORMAT_R16G16B16X16_UNORM:
+ case PIPE_FORMAT_R16G16B16X16_SNORM:
+ case PIPE_FORMAT_R16G16B16X16_FLOAT:
+ case PIPE_FORMAT_R16G16B16X16_UINT:
+ case PIPE_FORMAT_R16G16B16X16_SINT:
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
/* 128-bit buffers. */
case PIPE_FORMAT_R32G32B32A32_UNORM:
case PIPE_FORMAT_R32G32B32A32_SINT:
case PIPE_FORMAT_R32G32B32A32_UINT:
+ case PIPE_FORMAT_R32G32B32X32_FLOAT:
+ case PIPE_FORMAT_R32G32B32X32_UINT:
+ case PIPE_FORMAT_R32G32B32X32_SINT:
return V_028C70_SWAP_STD;
default:
R600_ERR("unsupported colorswap format %d\n", format);
case PIPE_FORMAT_R8G8_SNORM:
case PIPE_FORMAT_R8G8_UINT:
case PIPE_FORMAT_R8G8_SINT:
+ case PIPE_FORMAT_R8A8_UNORM:
+ case PIPE_FORMAT_R8A8_SNORM:
+ case PIPE_FORMAT_R8A8_UINT:
+ case PIPE_FORMAT_R8A8_SINT:
return V_028C70_COLOR_8_8;
case PIPE_FORMAT_R16_UNORM:
case PIPE_FORMAT_R8G8B8A8_SNORM:
case PIPE_FORMAT_R8G8B8A8_UNORM:
case PIPE_FORMAT_R8G8B8X8_UNORM:
+ case PIPE_FORMAT_R8G8B8X8_SNORM:
+ case PIPE_FORMAT_R8G8B8X8_SRGB:
+ case PIPE_FORMAT_R8G8B8X8_UINT:
+ case PIPE_FORMAT_R8G8B8X8_SINT:
case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
case PIPE_FORMAT_X8B8G8R8_UNORM:
case PIPE_FORMAT_X8R8G8B8_UNORM:
case PIPE_FORMAT_R10G10B10X2_SNORM:
case PIPE_FORMAT_B10G10R10A2_UNORM:
case PIPE_FORMAT_B10G10R10A2_UINT:
+ case PIPE_FORMAT_B10G10R10X2_UNORM:
case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
return V_028C70_COLOR_2_10_10_10;
case PIPE_FORMAT_R16G16_FLOAT:
case PIPE_FORMAT_L16A16_FLOAT:
+ case PIPE_FORMAT_R16A16_FLOAT:
return V_028C70_COLOR_16_16_FLOAT;
case PIPE_FORMAT_R16G16_UNORM:
case PIPE_FORMAT_L16A16_SNORM:
case PIPE_FORMAT_L16A16_UINT:
case PIPE_FORMAT_L16A16_SINT:
+ case PIPE_FORMAT_R16A16_UNORM:
+ case PIPE_FORMAT_R16A16_SNORM:
+ case PIPE_FORMAT_R16A16_UINT:
+ case PIPE_FORMAT_R16A16_SINT:
return V_028C70_COLOR_16_16;
case PIPE_FORMAT_R11G11B10_FLOAT:
case PIPE_FORMAT_R16G16B16A16_SINT:
case PIPE_FORMAT_R16G16B16A16_UNORM:
case PIPE_FORMAT_R16G16B16A16_SNORM:
+ case PIPE_FORMAT_R16G16B16X16_UNORM:
+ case PIPE_FORMAT_R16G16B16X16_SNORM:
+ case PIPE_FORMAT_R16G16B16X16_UINT:
+ case PIPE_FORMAT_R16G16B16X16_SINT:
return V_028C70_COLOR_16_16_16_16;
case PIPE_FORMAT_R16G16B16A16_FLOAT:
+ case PIPE_FORMAT_R16G16B16X16_FLOAT:
return V_028C70_COLOR_16_16_16_16_FLOAT;
case PIPE_FORMAT_R32G32_FLOAT:
case PIPE_FORMAT_L32A32_FLOAT:
+ case PIPE_FORMAT_R32A32_FLOAT:
return V_028C70_COLOR_32_32_FLOAT;
case PIPE_FORMAT_R32G32_SINT:
case PIPE_FORMAT_R32G32B32A32_UNORM:
case PIPE_FORMAT_R32G32B32A32_SINT:
case PIPE_FORMAT_R32G32B32A32_UINT:
+ case PIPE_FORMAT_R32G32B32X32_UINT:
+ case PIPE_FORMAT_R32G32B32X32_SINT:
return V_028C70_COLOR_32_32_32_32;
case PIPE_FORMAT_R32G32B32A32_FLOAT:
+ case PIPE_FORMAT_R32G32B32X32_FLOAT:
return V_028C70_COLOR_32_32_32_32_FLOAT;
/* YUV buffers. */
dsa->valuemask[1] = state->stencil[1].valuemask;
dsa->writemask[0] = state->stencil[0].writemask;
dsa->writemask[1] = state->stencil[1].writemask;
+ dsa->zwritemask = state->depth.writemask;
db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
if (rctx->chip_class == CAYMAN) {
r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
- S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
+ S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
} else {
r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
- S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
+ S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
}
return ss;
}
+static struct pipe_sampler_view *
+texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
+ unsigned width0, unsigned height0)
+
+{
+ struct pipe_context *ctx = view->base.context;
+ struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
+ uint64_t va;
+ int stride = util_format_get_blocksize(view->base.format);
+ unsigned format, num_format, format_comp, endian;
+ unsigned swizzle_res;
+ unsigned char swizzle[4];
+ const struct util_format_description *desc;
+ unsigned offset = view->base.u.buf.first_element * stride;
+ unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
+
+ swizzle[0] = view->base.swizzle_r;
+ swizzle[1] = view->base.swizzle_g;
+ swizzle[2] = view->base.swizzle_b;
+ swizzle[3] = view->base.swizzle_a;
+
+ r600_vertex_data_type(view->base.format,
+ &format, &num_format, &format_comp,
+ &endian);
+
+ desc = util_format_description(view->base.format);
+
+ swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
+
+ va = r600_resource_va(ctx->screen, view->base.texture) + offset;
+ view->tex_resource = &tmp->resource;
+
+ view->skip_mip_address_reloc = true;
+ view->tex_resource_words[0] = va;
+ view->tex_resource_words[1] = size - 1;
+ view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
+ S_030008_STRIDE(stride) |
+ S_030008_DATA_FORMAT(format) |
+ S_030008_NUM_FORMAT_ALL(num_format) |
+ S_030008_FORMAT_COMP_ALL(format_comp) |
+ S_030008_SRF_MODE_ALL(1) |
+ S_030008_ENDIAN_SWAP(endian);
+ view->tex_resource_words[3] = swizzle_res;
+ /*
+ * in theory dword 4 is for number of elements, for use with resinfo,
+ * but it seems to utterly fail to work, the amd gpu shader analyser
+ * uses a const buffer to store the element sizes for buffer txq
+ */
+ view->tex_resource_words[4] = 0;
+ view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
+ view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
+ return &view->base;
+}
+
struct pipe_sampler_view *
evergreen_create_sampler_view_custom(struct pipe_context *ctx,
struct pipe_resource *texture,
struct r600_texture *tmp = (struct r600_texture*)texture;
unsigned format, endian;
uint32_t word4 = 0, yuv_format = 0, pitch = 0;
- unsigned char swizzle[4], array_mode = 0, tile_type = 0;
+ unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
unsigned height, depth, width;
unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
+ enum pipe_format pipe_format = state->format;
+ struct radeon_surface_level *surflevel;
if (view == NULL)
return NULL;
view->base.reference.count = 1;
view->base.context = ctx;
+ if (texture->target == PIPE_BUFFER)
+ return texture_buffer_sampler_view(view, width0, height0);
+
swizzle[0] = state->swizzle_r;
swizzle[1] = state->swizzle_g;
swizzle[2] = state->swizzle_b;
swizzle[3] = state->swizzle_a;
- format = r600_translate_texformat(ctx->screen, state->format,
+ tile_split = tmp->surface.tile_split;
+ surflevel = tmp->surface.level;
+
+ /* Texturing with separate depth and stencil. */
+ if (tmp->is_depth && !tmp->is_flushing_texture) {
+ switch (pipe_format) {
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+ pipe_format = PIPE_FORMAT_Z32_FLOAT;
+ break;
+ case PIPE_FORMAT_X8Z24_UNORM:
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+ /* Z24 is always stored like this. */
+ pipe_format = PIPE_FORMAT_Z24X8_UNORM;
+ break;
+ case PIPE_FORMAT_X24S8_UINT:
+ case PIPE_FORMAT_S8X24_UINT:
+ case PIPE_FORMAT_X32_S8X24_UINT:
+ pipe_format = PIPE_FORMAT_S8_UINT;
+ tile_split = tmp->surface.stencil_tile_split;
+ surflevel = tmp->surface.stencil_level;
+ break;
+ default:;
+ }
+ }
+
+ format = r600_translate_texformat(ctx->screen, pipe_format,
swizzle,
&word4, &yuv_format);
assert(format != ~0);
return NULL;
}
- if (tmp->is_depth && !tmp->is_flushing_texture) {
- if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
- FREE(view);
- return NULL;
- }
- tmp = tmp->flushed_depth_texture;
- }
-
endian = r600_colorformat_endian_swap(format);
width = width0;
height = height0;
- depth = tmp->surface.level[0].npix_z;
- pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
- tile_type = tmp->tile_type;
+ depth = texture->depth0;
+ pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
+ non_disp_tiling = tmp->non_disp_tiling;
- switch (tmp->surface.level[0].mode) {
+ switch (surflevel[0].mode) {
case RADEON_SURF_MODE_LINEAR_ALIGNED:
array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
break;
array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
break;
}
- tile_split = tmp->surface.tile_split;
macro_aspect = tmp->surface.mtilea;
bankw = tmp->surface.bankw;
bankh = tmp->surface.bankh;
/* 128 bit formats require tile type = 1 */
if (rscreen->chip_class == CAYMAN) {
- if (util_format_get_blocksize(state->format) >= 16)
- tile_type = 1;
+ if (util_format_get_blocksize(pipe_format) >= 16)
+ non_disp_tiling = 1;
}
nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
depth = texture->array_size;
} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
depth = texture->array_size;
- }
+ } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
+ depth = texture->array_size / 6;
view->tex_resource = &tmp->resource;
view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
S_030000_PITCH((pitch / 8) - 1) |
S_030000_TEX_WIDTH(width - 1));
if (rscreen->chip_class == CAYMAN)
- view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
+ view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
else
- view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
+ view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
S_030004_TEX_DEPTH(depth - 1) |
S_030004_ARRAY_MODE(array_mode));
- view->tex_resource_words[2] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
+ view->tex_resource_words[2] = (surflevel[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
/* TEX_RESOURCE_WORD3.MIP_ADDRESS */
if (texture->nr_samples > 1 && rscreen->msaa_texture_support == MSAA_TEXTURE_COMPRESSED) {
view->tex_resource_words[3] = (tmp->fmask_offset + r600_resource_va(ctx->screen, texture)) >> 8;
}
} else if (state->u.tex.last_level && texture->nr_samples <= 1) {
- view->tex_resource_words[3] = (tmp->surface.level[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
+ view->tex_resource_words[3] = (surflevel[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
} else {
- view->tex_resource_words[3] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
+ view->tex_resource_words[3] = (surflevel[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
}
view->tex_resource_words[4] = (word4 |
S_03001C_BANK_WIDTH(bankw) |
S_03001C_BANK_HEIGHT(bankh) |
S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
- S_03001C_NUM_BANKS(nbanks);
+ S_03001C_NUM_BANKS(nbanks) |
+ S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
return &view->base;
}
static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->cs;
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
struct pipe_clip_state *state = &rctx->clip_state.state;
r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->cs;
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
struct pipe_scissor_state *state = &rctx->scissor.scissor;
uint32_t tl, br;
* elements. */
surf->cb_color_dim = pipe_buffer->width0;
+ /* Set the buffer range the GPU will have access to: */
+ util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
+ 0, pipe_buffer->width0);
+
surf->cb_color_cmask = surf->cb_color_base;
surf->cb_color_cmask_slice = 0;
surf->cb_color_fmask = surf->cb_color_base;
unsigned color_info, color_attrib, color_dim = 0;
unsigned format, swap, ntype, endian;
uint64_t offset, base_offset;
- unsigned tile_type, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
+ unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
const struct util_format_description *desc;
int i;
bool blend_clamp = 0, blend_bypass = 0;
- if (rtex->is_depth && !rtex->is_flushing_texture) {
- r600_init_flushed_depth_texture(&rctx->context, pipe_tex, NULL);
- rtex = rtex->flushed_depth_texture;
- assert(rtex);
- }
-
offset = rtex->surface.level[level].offset;
if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
offset += rtex->surface.level[level].slice_size *
switch (rtex->surface.level[level].mode) {
case RADEON_SURF_MODE_LINEAR_ALIGNED:
color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
- tile_type = 1;
+ non_disp_tiling = 1;
break;
case RADEON_SURF_MODE_1D:
color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
- tile_type = rtex->tile_type;
+ non_disp_tiling = rtex->non_disp_tiling;
break;
case RADEON_SURF_MODE_2D:
color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
- tile_type = rtex->tile_type;
+ non_disp_tiling = rtex->non_disp_tiling;
break;
case RADEON_SURF_MODE_LINEAR:
default:
color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
- tile_type = 1;
+ non_disp_tiling = 1;
break;
}
tile_split = rtex->surface.tile_split;
/* 128 bit formats require tile type = 1 */
if (rscreen->chip_class == CAYMAN) {
if (util_format_get_blocksize(surf->base.format) >= 16)
- tile_type = 1;
+ non_disp_tiling = 1;
}
nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
desc = util_format_description(surf->base.format);
S_028C74_BANK_WIDTH(bankw) |
S_028C74_BANK_HEIGHT(bankh) |
S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
- S_028C74_NON_DISP_TILING_ORDER(tile_type) |
+ S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
- if (rctx->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
- unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
- color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
- S_028C74_NUM_FRAGMENTS(log_samples);
+ if (rctx->chip_class == CAYMAN) {
+ color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
+ UTIL_FORMAT_SWIZZLE_1);
+
+ if (rtex->resource.b.b.nr_samples > 1) {
+ unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
+ color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
+ S_028C74_NUM_FRAGMENTS(log_samples);
+ }
}
ntype = V_028C70_NUMBER_UNORM;
switch (surf->base.format) {
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ case PIPE_FORMAT_X8Z24_UNORM:
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
surf->pa_su_poly_offset_db_fmt_cntl =
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
break;
}
if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
- uint64_t stencil_offset = rtex->surface.stencil_offset;
- unsigned i, stile_split = rtex->surface.stencil_tile_split;
+ uint64_t stencil_offset;
+ unsigned stile_split = rtex->surface.stencil_tile_split;
stile_split = eg_tile_split(stile_split);
+
+ stencil_offset = rtex->surface.stencil_level[level].offset;
stencil_offset += r600_resource_va(screen, surf->base.texture);
- stencil_offset += rtex->surface.level[level].offset / 4;
- stencil_offset >>= 8;
-
- /* We're guessing the stencil offset from the depth offset.
- * Make sure each mipmap level has a unique offset. */
- for (i = 1; i <= level; i++) {
- /* If two levels have the same address, add 256
- * to the offset of the smaller level. */
- if ((rtex->surface.level[i-1].offset / 4) >> 8 ==
- (rtex->surface.level[i].offset / 4) >> 8) {
- stencil_offset++;
- }
- }
- surf->db_stencil_base = stencil_offset;
+ surf->db_stencil_base = stencil_offset >> 8;
surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
S_028044_TILE_SPLIT(stile_split);
} else {
S_028044_FORMAT(V_028044_STENCIL_8);
}
+ surf->htile_enabled = 0;
+ /* use htile only for first level */
+ if (rtex->htile && !level) {
+ uint64_t va = r600_resource_va(&rctx->screen->screen, &rtex->htile->b.b);
+ surf->htile_enabled = 1;
+ surf->db_htile_data_base = va >> 8;
+ surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
+ S_028ABC_HTILE_HEIGHT(1) |
+ S_028ABC_FULL_CACHE(1) |
+ S_028ABC_LINEAR(1);
+ surf->db_depth_info |= S_028040_TILE_SURFACE_ENABLE(1);
+ surf->db_preload_control = 0;
+ }
+
surf->depth_initialized = true;
}
uint32_t i, log_samples;
if (rctx->framebuffer.state.nr_cbufs) {
- rctx->flags |= R600_CONTEXT_CB_FLUSH;
+ rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
if (rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
}
}
if (rctx->framebuffer.state.zsbuf) {
- rctx->flags |= R600_CONTEXT_DB_FLUSH;
+ rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
+
+ rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
+ if (rtex->htile) {
+ rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
+ }
}
util_copy_framebuffer_state(&rctx->framebuffer.state, state);
surf = (struct r600_surface*)state->cbufs[i];
rtex = (struct r600_texture*)surf->base.texture;
+ r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
+
if (!surf->color_initialized) {
evergreen_init_color_surface(rctx, surf);
}
if (state->zsbuf) {
surf = (struct r600_surface*)state->zsbuf;
+ r600_context_add_resource_size(ctx, state->zsbuf->texture);
+
if (!surf->depth_initialized) {
evergreen_init_depth_surface(rctx, surf);
}
rctx->poly_offset_state.zs_format = state->zsbuf->format;
rctx->poly_offset_state.atom.dirty = true;
}
+
+ if (rctx->db_state.rsurf != surf) {
+ rctx->db_state.rsurf = surf;
+ rctx->db_state.atom.dirty = true;
+ rctx->db_misc_state.atom.dirty = true;
+ }
+ } else if (rctx->db_state.rsurf) {
+ rctx->db_state.rsurf = NULL;
+ rctx->db_state.atom.dirty = true;
+ rctx->db_misc_state.atom.dirty = true;
}
if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
(((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
(((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
+/* 2xMSAA
+ * There are two locations (-4, 4), (4, -4). */
+static uint32_t sample_locs_2x[] = {
+ FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
+ FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
+ FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
+ FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
+};
+static unsigned max_dist_2x = 4;
+/* 4xMSAA
+ * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
+static uint32_t sample_locs_4x[] = {
+ FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
+ FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
+ FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
+ FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
+};
+static unsigned max_dist_4x = 6;
+/* 8xMSAA */
+static uint32_t sample_locs_8x[] = {
+ FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
+ FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
+ FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
+ FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
+ FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
+ FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
+ FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
+ FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
+};
+static unsigned max_dist_8x = 7;
+
+static void evergreen_get_sample_position(struct pipe_context *ctx,
+ unsigned sample_count,
+ unsigned sample_index,
+ float *out_value)
+{
+ int offset, index;
+ struct {
+ int idx:4;
+ } val;
+ switch (sample_count) {
+ case 1:
+ default:
+ out_value[0] = out_value[1] = 0.5;
+ break;
+ case 2:
+ offset = 4 * (sample_index * 2);
+ val.idx = (sample_locs_2x[0] >> offset) & 0xf;
+ out_value[0] = (float)(val.idx + 8) / 16.0f;
+ val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
+ out_value[1] = (float)(val.idx + 8) / 16.0f;
+ break;
+ case 4:
+ offset = 4 * (sample_index * 2);
+ val.idx = (sample_locs_4x[0] >> offset) & 0xf;
+ out_value[0] = (float)(val.idx + 8) / 16.0f;
+ val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
+ out_value[1] = (float)(val.idx + 8) / 16.0f;
+ break;
+ case 8:
+ offset = 4 * (sample_index % 4 * 2);
+ index = (sample_index / 4);
+ val.idx = (sample_locs_8x[index] >> offset) & 0xf;
+ out_value[0] = (float)(val.idx + 8) / 16.0f;
+ val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
+ out_value[1] = (float)(val.idx + 8) / 16.0f;
+ break;
+ }
+}
+
static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples)
{
- /* 2xMSAA
- * There are two locations (-4, 4), (4, -4). */
- static uint32_t sample_locs_2x[] = {
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
- };
- static unsigned max_dist_2x = 4;
- /* 4xMSAA
- * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
- static uint32_t sample_locs_4x[] = {
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
- };
- static unsigned max_dist_4x = 6;
- /* 8xMSAA */
- static uint32_t sample_locs_8x[] = {
- FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
- FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
- FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
- FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
- FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
- FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
- FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
- FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
- };
- static unsigned max_dist_8x = 7;
-
- struct radeon_winsys_cs *cs = rctx->cs;
+
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
unsigned max_dist = 0;
switch (nr_samples) {
}
}
+/* Cayman 8xMSAA */
+static uint32_t cm_sample_locs_8x[] = {
+ FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
+ FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
+ FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
+ FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
+ FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
+ FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
+ FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
+ FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
+};
+static unsigned cm_max_dist_8x = 8;
+/* Cayman 16xMSAA */
+static uint32_t cm_sample_locs_16x[] = {
+ FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
+ FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
+ FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
+ FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
+ FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
+ FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
+ FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
+ FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
+ FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
+ FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
+ FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
+ FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
+ FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
+ FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
+ FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
+ FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
+};
+static unsigned cm_max_dist_16x = 8;
+static void cayman_get_sample_position(struct pipe_context *ctx,
+ unsigned sample_count,
+ unsigned sample_index,
+ float *out_value)
+{
+ int offset, index;
+ struct {
+ int idx:4;
+ } val;
+ switch (sample_count) {
+ case 1:
+ default:
+ out_value[0] = out_value[1] = 0.5;
+ break;
+ case 2:
+ offset = 4 * (sample_index * 2);
+ val.idx = (sample_locs_2x[0] >> offset) & 0xf;
+ out_value[0] = (float)(val.idx + 8) / 16.0f;
+ val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
+ out_value[1] = (float)(val.idx + 8) / 16.0f;
+ break;
+ case 4:
+ offset = 4 * (sample_index * 2);
+ val.idx = (sample_locs_4x[0] >> offset) & 0xf;
+ out_value[0] = (float)(val.idx + 8) / 16.0f;
+ val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
+ out_value[1] = (float)(val.idx + 8) / 16.0f;
+ break;
+ case 8:
+ offset = 4 * (sample_index % 4 * 2);
+ index = (sample_index / 4) * 4;
+ val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
+ out_value[0] = (float)(val.idx + 8) / 16.0f;
+ val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
+ out_value[1] = (float)(val.idx + 8) / 16.0f;
+ break;
+ case 16:
+ offset = 4 * (sample_index % 4 * 2);
+ index = (sample_index / 4) * 4;
+ val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
+ out_value[0] = (float)(val.idx + 8) / 16.0f;
+ val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
+ out_value[1] = (float)(val.idx + 8) / 16.0f;
+ break;
+ }
+}
+
static void cayman_emit_msaa_state(struct r600_context *rctx, int nr_samples)
{
- /* 2xMSAA
- * There are two locations (-4, 4), (4, -4). */
- static uint32_t sample_locs_2x[] = {
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
- };
- static unsigned max_dist_2x = 4;
- /* 4xMSAA
- * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
- static uint32_t sample_locs_4x[] = {
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
- };
- static unsigned max_dist_4x = 6;
- /* 8xMSAA */
- static uint32_t sample_locs_8x[] = {
- FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
- FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
- FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
- FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
- FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
- FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
- FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
- FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
- };
- static unsigned max_dist_8x = 8;
- /* 16xMSAA */
- static uint32_t sample_locs_16x[] = {
- FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
- FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
- FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
- FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
- FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
- FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
- FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
- FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
- FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
- FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
- FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
- FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
- FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
- FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
- FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
- FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
- };
- static unsigned max_dist_16x = 8;
-
- struct radeon_winsys_cs *cs = rctx->cs;
+
+
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
unsigned max_dist = 0;
switch (nr_samples) {
break;
case 8:
r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
- r600_write_value(cs, sample_locs_8x[0]);
- r600_write_value(cs, sample_locs_8x[4]);
+ r600_write_value(cs, cm_sample_locs_8x[0]);
+ r600_write_value(cs, cm_sample_locs_8x[4]);
r600_write_value(cs, 0);
r600_write_value(cs, 0);
- r600_write_value(cs, sample_locs_8x[1]);
- r600_write_value(cs, sample_locs_8x[5]);
+ r600_write_value(cs, cm_sample_locs_8x[1]);
+ r600_write_value(cs, cm_sample_locs_8x[5]);
r600_write_value(cs, 0);
r600_write_value(cs, 0);
- r600_write_value(cs, sample_locs_8x[2]);
- r600_write_value(cs, sample_locs_8x[6]);
+ r600_write_value(cs, cm_sample_locs_8x[2]);
+ r600_write_value(cs, cm_sample_locs_8x[6]);
r600_write_value(cs, 0);
r600_write_value(cs, 0);
- r600_write_value(cs, sample_locs_8x[3]);
- r600_write_value(cs, sample_locs_8x[7]);
- max_dist = max_dist_8x;
+ r600_write_value(cs, cm_sample_locs_8x[3]);
+ r600_write_value(cs, cm_sample_locs_8x[7]);
+ max_dist = cm_max_dist_8x;
break;
case 16:
r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
- r600_write_value(cs, sample_locs_16x[0]);
- r600_write_value(cs, sample_locs_16x[4]);
- r600_write_value(cs, sample_locs_16x[8]);
- r600_write_value(cs, sample_locs_16x[12]);
- r600_write_value(cs, sample_locs_16x[1]);
- r600_write_value(cs, sample_locs_16x[5]);
- r600_write_value(cs, sample_locs_16x[9]);
- r600_write_value(cs, sample_locs_16x[13]);
- r600_write_value(cs, sample_locs_16x[2]);
- r600_write_value(cs, sample_locs_16x[6]);
- r600_write_value(cs, sample_locs_16x[10]);
- r600_write_value(cs, sample_locs_16x[14]);
- r600_write_value(cs, sample_locs_16x[3]);
- r600_write_value(cs, sample_locs_16x[7]);
- r600_write_value(cs, sample_locs_16x[11]);
- r600_write_value(cs, sample_locs_16x[15]);
- max_dist = max_dist_16x;
+ r600_write_value(cs, cm_sample_locs_16x[0]);
+ r600_write_value(cs, cm_sample_locs_16x[4]);
+ r600_write_value(cs, cm_sample_locs_16x[8]);
+ r600_write_value(cs, cm_sample_locs_16x[12]);
+ r600_write_value(cs, cm_sample_locs_16x[1]);
+ r600_write_value(cs, cm_sample_locs_16x[5]);
+ r600_write_value(cs, cm_sample_locs_16x[9]);
+ r600_write_value(cs, cm_sample_locs_16x[13]);
+ r600_write_value(cs, cm_sample_locs_16x[2]);
+ r600_write_value(cs, cm_sample_locs_16x[6]);
+ r600_write_value(cs, cm_sample_locs_16x[10]);
+ r600_write_value(cs, cm_sample_locs_16x[14]);
+ r600_write_value(cs, cm_sample_locs_16x[3]);
+ r600_write_value(cs, cm_sample_locs_16x[7]);
+ r600_write_value(cs, cm_sample_locs_16x[11]);
+ r600_write_value(cs, cm_sample_locs_16x[15]);
+ max_dist = cm_max_dist_16x;
break;
}
static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->cs;
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
unsigned nr_cbufs = state->nr_cbufs;
unsigned i, tl, br;
/* Colorbuffers. */
for (i = 0; i < nr_cbufs; i++) {
struct r600_surface *cb = (struct r600_surface*)state->cbufs[i];
- unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)cb->base.texture,
+ unsigned reloc = r600_context_bo_reloc(rctx,
+ &rctx->rings.gfx,
+ (struct r600_resource*)cb->base.texture,
RADEON_USAGE_READWRITE);
r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 11);
((struct r600_surface*)state->cbufs[0])->cb_color_info);
if (!rctx->keep_tiling_flags) {
- unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)state->cbufs[0]->texture,
+ unsigned reloc = r600_context_bo_reloc(rctx,
+ &rctx->rings.gfx,
+ (struct r600_resource*)state->cbufs[0]->texture,
RADEON_USAGE_READWRITE);
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
/* ZS buffer. */
if (state->zsbuf) {
struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
- unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)state->zsbuf->texture,
+ unsigned reloc = r600_context_bo_reloc(rctx,
+ &rctx->rings.gfx,
+ (struct r600_resource*)state->zsbuf->texture,
RADEON_USAGE_READWRITE);
r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
{
- struct radeon_winsys_cs *cs = rctx->cs;
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
float offset_units = state->offset_units;
float offset_scale = state->offset_scale;
switch (state->zs_format) {
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ case PIPE_FORMAT_X8Z24_UNORM:
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
offset_units *= 2.0f;
break;
case PIPE_FORMAT_Z16_UNORM:
static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->cs;
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
}
+static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct r600_db_state *a = (struct r600_db_state*)atom;
+
+ if (a->rsurf && a->rsurf->htile_enabled) {
+ struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
+ unsigned reloc_idx;
+
+ r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear));
+ r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
+ r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
+ r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
+ reloc_idx = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rtex->htile, RADEON_USAGE_READWRITE);
+ cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+ cs->buf[cs->cdw++] = reloc_idx;
+ } else {
+ r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
+ r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
+ }
+}
+
static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->cs;
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
unsigned db_render_control = 0;
unsigned db_count_control = 0;
unsigned db_render_override =
- S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
}
db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
}
-
+ /* FIXME we should be able to use hyperz even if we are not writing to
+ * zbuffer but somehow this trigger GPU lockup. See :
+ *
+ * https://bugs.freedesktop.org/show_bug.cgi?id=60848
+ *
+ * Disable hyperz for now if not writing to zbuffer.
+ */
+ if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled && rctx->zwritemask) {
+ /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
+ db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
+ /* This is to fix a lockup when hyperz and alpha test are enabled at
+ * the same time somehow GPU get confuse on which order to pick for
+ * z test
+ */
+ if (rctx->alphatest_state.sx_alpha_test_control) {
+ db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
+ }
+ } else {
+ db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
+ }
if (a->flush_depthstencil_through_cb) {
assert(a->copy_depth || a->copy_stencil);
S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
S_028000_COPY_CENTROID(1) |
S_028000_COPY_SAMPLE(a->copy_sample);
+ } else if (a->flush_depthstencil_in_place) {
+ db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(1) |
+ S_028000_STENCIL_COMPRESS_DISABLE(1);
+ db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
+ }
+ if (a->htile_clear) {
+ /* FIXME we might want to disable cliprect here */
+ db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
}
r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
unsigned resource_offset,
unsigned pkt_flags)
{
- struct radeon_winsys_cs *cs = rctx->cs;
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
uint32_t dirty_mask = state->dirty_mask;
while (dirty_mask) {
r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
- r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
+ r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
}
state->dirty_mask = 0;
}
struct r600_constbuf_state *state,
unsigned buffer_id_base,
unsigned reg_alu_constbuf_size,
- unsigned reg_alu_const_cache)
+ unsigned reg_alu_const_cache,
+ unsigned pkt_flags)
{
- struct radeon_winsys_cs *cs = rctx->cs;
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
uint32_t dirty_mask = state->dirty_mask;
while (dirty_mask) {
va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
va += cb->buffer_offset;
- r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
- ALIGN_DIVUP(cb->buffer_size >> 4, 16));
- r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
+ r600_write_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
+ ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags);
+ r600_write_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
+ pkt_flags);
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
- r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
+ r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
+ r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
- r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
+ r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
r600_write_value(cs, va); /* RESOURCEi_WORD0 */
r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
- r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
+ r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
+ r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
dirty_mask &= ~(1 << buffer_index);
}
{
evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
- R_028980_ALU_CONST_CACHE_VS_0);
+ R_028980_ALU_CONST_CACHE_VS_0,
+ 0 /* PKT3 flags */);
}
static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
{
evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
- R_0289C0_ALU_CONST_CACHE_GS_0);
+ R_0289C0_ALU_CONST_CACHE_GS_0,
+ 0 /* PKT3 flags */);
}
static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
{
evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
- R_028940_ALU_CONST_CACHE_PS_0);
+ R_028940_ALU_CONST_CACHE_PS_0,
+ 0 /* PKT3 flags */);
+}
+
+static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
+{
+ evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE], 816,
+ R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
+ R_028F40_ALU_CONST_CACHE_LS_0,
+ RADEON_CP_PACKET3_COMPUTE_MODE);
}
static void evergreen_emit_sampler_views(struct r600_context *rctx,
struct r600_samplerview_state *state,
unsigned resource_id_base)
{
- struct radeon_winsys_cs *cs = rctx->cs;
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
uint32_t dirty_mask = state->dirty_mask;
while (dirty_mask) {
r600_write_value(cs, (resource_id_base + resource_index) * 8);
r600_write_array(cs, 8, rview->tex_resource_words);
- reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
+ reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rview->tex_resource,
RADEON_USAGE_READ);
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
r600_write_value(cs, reloc);
unsigned resource_id_base,
unsigned border_index_reg)
{
- struct radeon_winsys_cs *cs = rctx->cs;
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
uint32_t dirty_mask = texinfo->states.dirty_mask;
while (dirty_mask) {
struct r600_sample_mask *s = (struct r600_sample_mask*)a;
uint8_t mask = s->sample_mask;
- r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
+ r600_write_context_reg(rctx->rings.gfx.cs, R_028C3C_PA_SC_AA_MASK,
mask | (mask << 8) | (mask << 16) | (mask << 24));
}
static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
{
struct r600_sample_mask *s = (struct r600_sample_mask*)a;
- struct radeon_winsys_cs *cs = rctx->cs;
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
uint16_t mask = s->sample_mask;
r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
{
- struct radeon_winsys_cs *cs = rctx->cs;
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
struct r600_cso_state *state = (struct r600_cso_state*)a;
- struct r600_resource *shader = (struct r600_resource*)state->cso;
+ struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
r600_write_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
- r600_resource_va(rctx->context.screen, &shader->b.b) >> 8);
+ (r600_resource_va(rctx->context.screen, &shader->buffer->b.b) + shader->offset) >> 8);
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
- r600_write_value(cs, r600_context_bo_reloc(rctx, shader, RADEON_USAGE_READ));
-}
-
-void evergreen_init_state_functions(struct r600_context *rctx)
-{
- unsigned id = 4;
-
- /* !!!
- * To avoid GPU lockup registers must be emited in a specific order
- * (no kidding ...). The order below is important and have been
- * partialy infered from analyzing fglrx command stream.
- *
- * Don't reorder atom without carefully checking the effect (GPU lockup
- * or piglit regression).
- * !!!
- */
-
- r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
- /* shader const */
- r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
- r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
- r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
- /* shader program */
- r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
- /* sampler */
- r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
- r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
- r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
- /* resources */
- r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
- r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
- r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
- r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
- r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
-
- r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
- r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
-
- if (rctx->chip_class == EVERGREEN) {
- r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
- } else {
- r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
- }
- rctx->sample_mask.sample_mask = ~0;
-
- r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
- r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
- r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
- r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
- r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
- r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
- r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
- r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
- r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
- r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
- r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 4);
- r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
- r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
- r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
-
- rctx->context.create_blend_state = evergreen_create_blend_state;
- rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
- rctx->context.create_rasterizer_state = evergreen_create_rs_state;
- rctx->context.create_sampler_state = evergreen_create_sampler_state;
- rctx->context.create_sampler_view = evergreen_create_sampler_view;
- rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
- rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
- rctx->context.set_scissor_state = evergreen_set_scissor_state;
- evergreen_init_compute_state_functions(rctx);
+ r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, shader->buffer, RADEON_USAGE_READ));
}
void cayman_init_common_regs(struct r600_command_buffer *cb,
r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
- r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
- r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
- r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
+ r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
}
+ r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
+ r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
+ r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
+ r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
+ r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
+ r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
+ r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
+
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
}
r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
- r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
- r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
- r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
+ r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
}
+ r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
+ r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
+ r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
+ r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
+ r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
+ r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
+ r600_store_context_reg(cb, R_0288EC_SQ_LDS_ALLOC_PS, 0);
+ r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
+
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
}
-void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_pipe_state *rstate = &shader->rstate;
+ struct r600_command_buffer *cb = &shader->command_buffer;
struct r600_shader *rshader = &shader->shader;
- unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
+ unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
int pos_index = -1, face_index = -1;
int ninterp = 0;
boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
- unsigned spi_baryc_cntl, sid, tmp, idx = 0;
+ unsigned spi_baryc_cntl, sid, tmp, num = 0;
unsigned z_export = 0, stencil_export = 0;
unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
+ uint32_t spi_ps_input_cntl[32];
- rstate->nregs = 0;
+ if (!cb->buf) {
+ r600_init_command_buffer(cb, 64);
+ } else {
+ cb->num_dw = 0;
+ }
- db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
for (i = 0; i < rshader->ninput; i++) {
/* evergreen NUM_INTERP only contains values interpolated into the LDS,
POSITION goes via GPRs from the SC so isn't counted */
sid = rshader->input[i].spi_sid;
if (sid) {
-
tmp = S_028644_SEMANTIC(sid);
if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
tmp |= S_028644_PT_SPRITE_TEX(1);
}
- r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
- tmp);
-
- idx++;
+ spi_ps_input_cntl[num++] = tmp;
}
}
+ r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
+ r600_store_array(cb, num, spi_ps_input_cntl);
+
for (i = 0; i < rshader->noutput; i++) {
if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
z_export = 1;
spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
- spi_input_z |= 1;
+ spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
}
spi_ps_in_control_1 = 0;
spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
- r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
- spi_ps_in_control_0);
- r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
- spi_ps_in_control_1);
- r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
- 0);
- r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
- r600_pipe_state_add_reg(rstate,
- R_0286E0_SPI_BARYC_CNTL,
- spi_baryc_cntl);
-
- r600_pipe_state_add_reg_bo(rstate,
- R_028840_SQ_PGM_START_PS,
- r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
- shader->bo, RADEON_USAGE_READ);
- r600_pipe_state_add_reg(rstate,
- R_028844_SQ_PGM_RESOURCES_PS,
- S_028844_NUM_GPRS(rshader->bc.ngpr) |
- S_028844_PRIME_CACHE_ON_DRAW(1) |
- S_028844_STACK_SIZE(rshader->bc.nstack));
- r600_pipe_state_add_reg(rstate,
- R_02884C_SQ_PGM_EXPORTS_PS,
- exports_ps);
+ r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
+ r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
+ r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
+
+ r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
+ r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
+ r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
+
+ r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
+ r600_store_value(cb, r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
+ r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
+ S_028844_NUM_GPRS(rshader->bc.ngpr) |
+ S_028844_PRIME_CACHE_ON_DRAW(1) |
+ S_028844_STACK_SIZE(rshader->bc.nstack));
+ /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
shader->db_shader_control = db_shader_control;
shader->ps_depth_export = z_export | stencil_export;
shader->flatshade = rctx->rasterizer->flatshade;
}
-void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
{
- struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_pipe_state *rstate = &shader->rstate;
+ struct r600_command_buffer *cb = &shader->command_buffer;
struct r600_shader *rshader = &shader->shader;
unsigned spi_vs_out_id[10] = {};
unsigned i, tmp, nparams = 0;
- /* clear previous register */
- rstate->nregs = 0;
-
for (i = 0; i < rshader->noutput; i++) {
if (rshader->output[i].spi_sid) {
tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
}
}
+ r600_init_command_buffer(cb, 32);
+
+ r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
for (i = 0; i < 10; i++) {
- r600_pipe_state_add_reg(rstate,
- R_02861C_SPI_VS_OUT_ID_0 + i * 4,
- spi_vs_out_id[i]);
+ r600_store_value(cb, spi_vs_out_id[i]);
}
/* Certain attributes (position, psize, etc.) don't count as params.
if (nparams < 1)
nparams = 1;
- r600_pipe_state_add_reg(rstate,
- R_0286C4_SPI_VS_OUT_CONFIG,
- S_0286C4_VS_EXPORT_COUNT(nparams - 1));
- r600_pipe_state_add_reg(rstate,
- R_028860_SQ_PGM_RESOURCES_VS,
- S_028860_NUM_GPRS(rshader->bc.ngpr) |
- S_028860_STACK_SIZE(rshader->bc.nstack));
- r600_pipe_state_add_reg_bo(rstate,
- R_02885C_SQ_PGM_START_VS,
- r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
- shader->bo, RADEON_USAGE_READ);
+ r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
+ S_0286C4_VS_EXPORT_COUNT(nparams - 1));
+ r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
+ S_028860_NUM_GPRS(rshader->bc.ngpr) |
+ S_028860_STACK_SIZE(rshader->bc.nstack));
+ r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
+ r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
+ /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
shader->pa_cl_vs_out_cntl =
S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
V_02880C_EXPORT_DB_FULL) |
S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
+ /* When alpha test is enabled we can't trust the hw to make the proper
+ * decision on the order in which ztest should be run related to fragment
+ * shader execution.
+ *
+ * If alpha test is enabled perform early z rejection (RE_Z) but don't early
+ * write to the zbuffer. Write to zbuffer is delayed after fragment shader
+ * execution and thus after alpha test so if discarded by the alpha test
+ * the z value is not written.
+ * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
+ * get a hang unless you flush the DB in between. For now just use
+ * LATE_Z.
+ */
+ if (rctx->alphatest_state.sx_alpha_test_control) {
+ db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
+ } else {
+ db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+ }
+
if (db_shader_control != rctx->db_misc_state.db_shader_control) {
rctx->db_misc_state.db_shader_control = db_shader_control;
rctx->db_misc_state.atom.dirty = true;
}
}
+
+static void evergreen_dma_copy_tile(struct r600_context *rctx,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ unsigned dst_x,
+ unsigned dst_y,
+ unsigned dst_z,
+ struct pipe_resource *src,
+ unsigned src_level,
+ unsigned src_x,
+ unsigned src_y,
+ unsigned src_z,
+ unsigned copy_height,
+ unsigned pitch,
+ unsigned bpp)
+{
+ struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
+ struct r600_texture *rsrc = (struct r600_texture*)src;
+ struct r600_texture *rdst = (struct r600_texture*)dst;
+ unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
+ unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
+ unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
+ uint64_t base, addr;
+
+ /* make sure that the dma ring is only one active */
+ rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
+
+ dst_mode = rdst->surface.level[dst_level].mode;
+ src_mode = rsrc->surface.level[src_level].mode;
+ /* downcast linear aligned to linear to simplify test */
+ src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
+ dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
+ assert(dst_mode != src_mode);
+
+ /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
+ if (util_format_has_depth(util_format_description(src->format)))
+ non_disp_tiling = 1;
+
+ y = 0;
+ sub_cmd = 0x8;
+ lbpp = util_logbase2(bpp);
+ pitch_tile_max = ((pitch / bpp) >> 3) - 1;
+ nbanks = eg_num_banks(rctx->screen->tiling_info.num_banks);
+
+ if (dst_mode == RADEON_SURF_MODE_LINEAR) {
+ /* T2L */
+ array_mode = evergreen_array_mode(src_mode);
+ slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6;
+ slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
+ /* linear height must be the same as the slice tile max height, it's ok even
+ * if the linear destination/source have smaller heigh as the size of the
+ * dma packet will be using the copy_height which is always smaller or equal
+ * to the linear height
+ */
+ height = rsrc->surface.level[src_level].npix_y;
+ detile = 1;
+ x = src_x;
+ y = src_y;
+ z = src_z;
+ base = rsrc->surface.level[src_level].offset;
+ addr = rdst->surface.level[dst_level].offset;
+ addr += rdst->surface.level[dst_level].slice_size * dst_z;
+ addr += dst_y * pitch + dst_x * bpp;
+ bank_h = eg_bank_wh(rsrc->surface.bankh);
+ bank_w = eg_bank_wh(rsrc->surface.bankw);
+ mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
+ tile_split = eg_tile_split(rsrc->surface.tile_split);
+ base += r600_resource_va(&rctx->screen->screen, src);
+ addr += r600_resource_va(&rctx->screen->screen, dst);
+ } else {
+ /* L2T */
+ array_mode = evergreen_array_mode(dst_mode);
+ slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6;
+ slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
+ /* linear height must be the same as the slice tile max height, it's ok even
+ * if the linear destination/source have smaller heigh as the size of the
+ * dma packet will be using the copy_height which is always smaller or equal
+ * to the linear height
+ */
+ height = rdst->surface.level[dst_level].npix_y;
+ detile = 0;
+ x = dst_x;
+ y = dst_y;
+ z = dst_z;
+ base = rdst->surface.level[dst_level].offset;
+ addr = rsrc->surface.level[src_level].offset;
+ addr += rsrc->surface.level[src_level].slice_size * src_z;
+ addr += src_y * pitch + src_x * bpp;
+ bank_h = eg_bank_wh(rdst->surface.bankh);
+ bank_w = eg_bank_wh(rdst->surface.bankw);
+ mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
+ tile_split = eg_tile_split(rdst->surface.tile_split);
+ base += r600_resource_va(&rctx->screen->screen, dst);
+ addr += r600_resource_va(&rctx->screen->screen, src);
+ }
+
+ size = (copy_height * pitch) >> 2;
+ ncopy = (size / 0x000fffff) + !!(size % 0x000fffff);
+ r600_need_dma_space(rctx, ncopy * 9);
+
+ for (i = 0; i < ncopy; i++) {
+ cheight = copy_height;
+ if (((cheight * pitch) >> 2) > 0x000fffff) {
+ cheight = (0x000fffff << 2) / pitch;
+ }
+ size = (cheight * pitch) >> 2;
+ /* emit reloc before writting cs so that cs is always in consistent state */
+ r600_context_bo_reloc(rctx, &rctx->rings.dma, &rsrc->resource, RADEON_USAGE_READ);
+ r600_context_bo_reloc(rctx, &rctx->rings.dma, &rdst->resource, RADEON_USAGE_WRITE);
+ cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
+ cs->buf[cs->cdw++] = base >> 8;
+ cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
+ (lbpp << 24) | (bank_h << 21) |
+ (bank_w << 18) | (mt_aspect << 16);
+ cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
+ cs->buf[cs->cdw++] = (slice_tile_max << 0);
+ cs->buf[cs->cdw++] = (x << 0) | (z << 18);
+ cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28);
+ cs->buf[cs->cdw++] = addr & 0xfffffffc;
+ cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
+ copy_height -= cheight;
+ addr += cheight * pitch;
+ y += cheight;
+ }
+}
+
+boolean evergreen_dma_blit(struct pipe_context *ctx,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ unsigned dst_x, unsigned dst_y, unsigned dst_z,
+ struct pipe_resource *src,
+ unsigned src_level,
+ const struct pipe_box *src_box)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_texture *rsrc = (struct r600_texture*)src;
+ struct r600_texture *rdst = (struct r600_texture*)dst;
+ unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
+ unsigned src_w, dst_w;
+
+ if (rctx->rings.dma.cs == NULL) {
+ return FALSE;
+ }
+ if (src->format != dst->format) {
+ return FALSE;
+ }
+
+ bpp = rdst->surface.bpe;
+ dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
+ src_pitch = rsrc->surface.level[src_level].pitch_bytes;
+ src_w = rsrc->surface.level[src_level].npix_x;
+ dst_w = rdst->surface.level[dst_level].npix_x;
+ copy_height = src_box->height / rsrc->surface.blk_h;
+
+ dst_mode = rdst->surface.level[dst_level].mode;
+ src_mode = rsrc->surface.level[src_level].mode;
+ /* downcast linear aligned to linear to simplify test */
+ src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
+ dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
+
+ if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
+ /* FIXME evergreen can do partial blit */
+ return FALSE;
+ }
+ /* the x test here are currently useless (because we don't support partial blit)
+ * but keep them around so we don't forget about those
+ */
+ if ((src_pitch & 0x7) || (src_box->x & 0x7) || (dst_x & 0x7) || (src_box->y & 0x7) || (dst_y & 0x7)) {
+ return FALSE;
+ }
+
+ /* 128 bpp surfaces require non_disp_tiling for both
+ * tiled and linear buffers on cayman. However, async
+ * DMA only supports it on the tiled side. As such
+ * the tile order is backwards after a L2T/T2L packet.
+ */
+ if ((rctx->chip_class == CAYMAN) &&
+ (src_mode != dst_mode) &&
+ (util_format_get_blocksize(src->format) >= 16)) {
+ return FALSE;
+ }
+
+ if (src_mode == dst_mode) {
+ uint64_t dst_offset, src_offset;
+ /* simple dma blit would do NOTE code here assume :
+ * src_box.x/y == 0
+ * dst_x/y == 0
+ * dst_pitch == src_pitch
+ */
+ src_offset= rsrc->surface.level[src_level].offset;
+ src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
+ src_offset += src_box->y * src_pitch + src_box->x * bpp;
+ dst_offset = rdst->surface.level[dst_level].offset;
+ dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
+ dst_offset += dst_y * dst_pitch + dst_x * bpp;
+ evergreen_dma_copy(rctx, dst, src, dst_offset, src_offset,
+ src_box->height * src_pitch);
+ } else {
+ evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
+ src, src_level, src_box->x, src_box->y, src_box->z,
+ copy_height, dst_pitch, bpp);
+ }
+ return TRUE;
+}
+
+void evergreen_init_state_functions(struct r600_context *rctx)
+{
+ unsigned id = 4;
+
+ /* !!!
+ * To avoid GPU lockup registers must be emited in a specific order
+ * (no kidding ...). The order below is important and have been
+ * partialy infered from analyzing fglrx command stream.
+ *
+ * Don't reorder atom without carefully checking the effect (GPU lockup
+ * or piglit regression).
+ * !!!
+ */
+
+ r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
+ /* shader const */
+ r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
+ r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
+ r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
+ r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
+ /* shader program */
+ r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
+ /* sampler */
+ r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
+ r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
+ r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
+ /* resources */
+ r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
+ r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
+ r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
+ r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
+ r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
+
+ r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
+
+ if (rctx->chip_class == EVERGREEN) {
+ r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
+ } else {
+ r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
+ }
+ rctx->sample_mask.sample_mask = ~0;
+
+ r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
+ r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
+ r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
+ r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
+ r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
+ r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
+ r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
+ r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
+ r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
+ r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
+ r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
+ r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 4);
+ r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
+ r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
+ r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
+ r600_init_atom(rctx, &rctx->streamout.begin_atom, id++, r600_emit_streamout_begin, 0);
+ r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
+ r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
+
+ rctx->context.create_blend_state = evergreen_create_blend_state;
+ rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
+ rctx->context.create_rasterizer_state = evergreen_create_rs_state;
+ rctx->context.create_sampler_state = evergreen_create_sampler_state;
+ rctx->context.create_sampler_view = evergreen_create_sampler_view;
+ rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
+ rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
+ rctx->context.set_scissor_state = evergreen_set_scissor_state;
+
+ if (rctx->chip_class == EVERGREEN)
+ rctx->context.get_sample_position = evergreen_get_sample_position;
+ else
+ rctx->context.get_sample_position = cayman_get_sample_position;
+ evergreen_init_compute_state_functions(rctx);
+}
projects / mesa.git / blobdiff