#include "util/u_pack_color.h"
#include "util/u_memory.h"
#include "util/u_framebuffer.h"
+#include "util/u_dual_blend.h"
static uint32_t eg_num_banks(uint32_t nbanks)
{
blend->cb_target_mask = target_mask;
r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
- color_control, NULL, 0);
-
+ color_control);
+ /* only have dual source on MRT0 */
+ blend->dual_src_blend = util_blend_state_is_dual(state, 0);
for (int i = 0; i < 8; i++) {
/* state->rt entries > 0 only written if independent blending */
const int j = state->independent_blend_enable ? i : 0;
}
}
for (int i = 0; i < 8; i++) {
- r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
}
return rstate;
alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
alpha_ref = fui(state->alpha.ref_value);
}
+ dsa->sx_alpha_test_control = alpha_test_control & 0xff;
dsa->alpha_ref = alpha_ref;
/* misc */
db_render_control = 0;
- r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
+ r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control);
return rstate;
}
tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
}
}
- r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
/* point size 12.4 fixed point */
tmp = (unsigned)(state->point_size * 8.0);
- r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
if (state->point_size_per_vertex) {
psize_min = util_get_min_point_size(state);
/* Divide by two, because 0.5 = 1 pixel. */
r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
- S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
- NULL, 0);
+ S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
tmp = (unsigned)state->line_width * 8;
- r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
- S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
- NULL, 0);
+ S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
if (rctx->chip_class == CAYMAN) {
r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
- S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
- NULL, 0);
+ S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
} else {
r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
- S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
- NULL, 0);
+ S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
}
- r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
S_028814_PROVOKING_VTX_LAST(prov_vtx) |
S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
S_028814_POLY_MODE(polygon_dual_mode) |
S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
- S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)),
- NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard), NULL, 0);
+ S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
+ r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
return rstate;
}
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- struct pipe_resource *cbuf;
+ struct pipe_constant_buffer cb;
if (rstate == NULL)
return;
for (int i = 0; i < 6; i++) {
r600_pipe_state_add_reg(rstate,
R_0285BC_PA_CL_UCP0_X + i * 16,
- fui(state->ucp[i][0]), NULL, 0);
+ fui(state->ucp[i][0]));
r600_pipe_state_add_reg(rstate,
R_0285C0_PA_CL_UCP0_Y + i * 16,
- fui(state->ucp[i][1]) , NULL, 0);
+ fui(state->ucp[i][1]) );
r600_pipe_state_add_reg(rstate,
R_0285C4_PA_CL_UCP0_Z + i * 16,
- fui(state->ucp[i][2]), NULL, 0);
+ fui(state->ucp[i][2]));
r600_pipe_state_add_reg(rstate,
R_0285C8_PA_CL_UCP0_W + i * 16,
- fui(state->ucp[i][3]), NULL, 0);
+ fui(state->ucp[i][3]));
}
free(rctx->states[R600_PIPE_STATE_CLIP]);
rctx->states[R600_PIPE_STATE_CLIP] = rstate;
r600_context_pipe_state_set(rctx, rstate);
- cbuf = pipe_user_buffer_create(ctx->screen,
- state->ucp,
- 4*4*8, /* 8*4 floats */
- PIPE_BIND_CONSTANT_BUFFER);
- r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
- pipe_resource_reference(&cbuf, NULL);
+ cb.buffer = NULL;
+ cb.user_buffer = state->ucp;
+ cb.buffer_offset = 0;
+ cb.buffer_size = 4*4*8;
+ r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
+ pipe_resource_reference(&cb.buffer, NULL);
}
static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
rstate->id = R600_PIPE_STATE_SCISSOR;
- r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl, NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br, NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
+ r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
free(rctx->states[R600_PIPE_STATE_SCISSOR]);
rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
rctx->viewport = *state;
rstate->id = R600_PIPE_STATE_VIEWPORT;
- r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
+ r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
+ r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
+ r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
+ r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
+ r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
format = r600_translate_colorformat(surf->base.format);
swap = r600_translate_colorswap(surf->base.format);
- if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
+ if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
endian = ENDIAN_NONE;
} else {
endian = r600_colorformat_endian_swap(format);
blend_bypass = 1;
}
+ if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT)
+ rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1);
+ else
+ rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS;
+
color_info |= S_028C70_FORMAT(format) |
S_028C70_COMP_SWAP(swap) |
S_028C70_BLEND_CLAMP(blend_clamp) |
}
rctx->alpha_ref_dirty = true;
+ if (cb == 0)
+ rctx->color0_format = color_info;
offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
offset >>= 8;
/* XXX handle enabling of CB beyond BASE8 which has different offset */
- r600_pipe_state_add_reg(rstate,
+ r600_pipe_state_add_reg_bo(rstate,
R_028C60_CB_COLOR0_BASE + cb * 0x3C,
offset, &rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate,
R_028C78_CB_COLOR0_DIM + cb * 0x3C,
- 0x0, NULL, 0);
- r600_pipe_state_add_reg(rstate,
+ 0x0);
+ r600_pipe_state_add_reg_bo(rstate,
R_028C70_CB_COLOR0_INFO + cb * 0x3C,
color_info, &rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate,
R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
- S_028C64_PITCH_TILE_MAX(pitch),
- NULL, 0);
+ S_028C64_PITCH_TILE_MAX(pitch));
r600_pipe_state_add_reg(rstate,
R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
- S_028C68_SLICE_TILE_MAX(slice),
- NULL, 0);
+ S_028C68_SLICE_TILE_MAX(slice));
if (!rscreen->use_surface_alloc) {
r600_pipe_state_add_reg(rstate,
R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
- 0x00000000, NULL, 0);
+ 0x00000000);
} else {
if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
r600_pipe_state_add_reg(rstate,
R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
- 0x00000000, NULL, 0);
+ 0x00000000);
} else {
r600_pipe_state_add_reg(rstate,
R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
- S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
- NULL, 0);
+ S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
}
}
- r600_pipe_state_add_reg(rstate,
+ r600_pipe_state_add_reg_bo(rstate,
R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
color_attrib,
&rtex->resource, RADEON_USAGE_READWRITE);
S_028040_BANK_HEIGHT(bankh) |
S_028040_MACRO_TILE_ASPECT(macro_aspect);
- r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
+ r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE,
offset, &rtex->resource, RADEON_USAGE_READWRITE);
- r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
+ r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE,
offset, &rtex->resource, RADEON_USAGE_READWRITE);
if (!rscreen->use_surface_alloc) {
r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
- 0x00000000, NULL, 0);
+ 0x00000000);
} else {
r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
- S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
- NULL, 0);
+ S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
}
if (rtex->stencil) {
stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
stencil_offset >>= 8;
- r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
+ r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
- r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
+ r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
- r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
+ r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1 | S_028044_TILE_SPLIT(stile_split),
&rtex->stencil->resource, RADEON_USAGE_READWRITE);
} else {
stencil_offset += rtex->surface.level[level].offset / 4;
stencil_offset >>= 8;
- r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
+ r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
stencil_offset, &rtex->resource,
RADEON_USAGE_READWRITE);
- r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
+ r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
stencil_offset, &rtex->resource,
RADEON_USAGE_READWRITE);
- r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
+ r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1 | S_028044_TILE_SPLIT(stile_split),
&rtex->resource,
RADEON_USAGE_READWRITE);
} else {
- r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
+ r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
offset, &rtex->resource,
RADEON_USAGE_READWRITE);
- r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
+ r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
offset, &rtex->resource,
RADEON_USAGE_READWRITE);
- r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
+ r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
0, NULL, RADEON_USAGE_READWRITE);
}
}
- r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, z_info,
+ r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, z_info,
&rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
- S_028058_PITCH_TILE_MAX(pitch),
- NULL, 0);
+ S_028058_PITCH_TILE_MAX(pitch));
r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
- S_02805C_SLICE_TILE_MAX(slice),
- NULL, 0);
+ S_02805C_SLICE_TILE_MAX(slice));
}
static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- uint32_t shader_mask, tl, br;
+ uint32_t tl, br;
if (rstate == NULL)
return;
evergreen_db(rctx, rstate, state);
}
- shader_mask = 0;
+ rctx->fb_cb_shader_mask = 0;
for (int i = 0; i < state->nr_cbufs; i++) {
- shader_mask |= 0xf << (i * 4);
+ rctx->fb_cb_shader_mask |= 0xf << (i * 4);
}
evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
r600_pipe_state_add_reg(rstate,
- R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
- NULL, 0);
+ R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
r600_pipe_state_add_reg(rstate,
- R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
- NULL, 0);
- r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
- shader_mask, NULL, 0);
+ R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
}
+static void evergreen_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ struct pipe_vertex_buffer *vb = rctx->vertex_buffer;
+ unsigned count = rctx->nr_vertex_buffers;
+ unsigned i;
+ uint64_t va;
+
+ for (i = 0; i < count; i++) {
+ struct r600_resource *rbuffer = (struct r600_resource*)vb[i].buffer;
+
+ if (!rbuffer) {
+ continue;
+ }
+
+ va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
+ va += vb[i].buffer_offset;
+
+ /* fetch resources start at index 992 */
+ r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
+ r600_write_value(cs, (992 + i) * 8);
+ r600_write_value(cs, va); /* RESOURCEi_WORD0 */
+ r600_write_value(cs, rbuffer->buf->size - vb[i].buffer_offset - 1); /* RESOURCEi_WORD1 */
+ r600_write_value(cs, /* RESOURCEi_WORD2 */
+ S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
+ S_030008_STRIDE(vb[i].stride) |
+ S_030008_BASE_ADDRESS_HI(va >> 32UL));
+ r600_write_value(cs, /* RESOURCEi_WORD3 */
+ S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
+ S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
+ S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
+ S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
+ r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
+ r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
+ r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
+ r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
+
+ r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+ r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
+ }
+}
+
+static void evergreen_emit_constant_buffer(struct r600_context *rctx,
+ struct r600_constbuf_state *state,
+ unsigned buffer_id_base,
+ unsigned reg_alu_constbuf_size,
+ unsigned reg_alu_const_cache)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ uint32_t dirty_mask = state->dirty_mask;
+
+ while (dirty_mask) {
+ struct pipe_constant_buffer *cb;
+ struct r600_resource *rbuffer;
+ uint64_t va;
+ unsigned buffer_index = ffs(dirty_mask) - 1;
+
+ cb = &state->cb[buffer_index];
+ rbuffer = (struct r600_resource*)cb->buffer;
+ assert(rbuffer);
+
+ va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
+ va += cb->buffer_offset;
+
+ r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
+ ALIGN_DIVUP(cb->buffer_size >> 4, 16));
+ r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
+
+ r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+ r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
+
+ r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
+ r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
+ r600_write_value(cs, va); /* RESOURCEi_WORD0 */
+ r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
+ r600_write_value(cs, /* RESOURCEi_WORD2 */
+ S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
+ S_030008_STRIDE(16) |
+ S_030008_BASE_ADDRESS_HI(va >> 32UL));
+ r600_write_value(cs, /* RESOURCEi_WORD3 */
+ S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
+ S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
+ S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
+ S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
+ r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
+ r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
+ r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
+ r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
+
+ r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+ r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
+
+ dirty_mask &= ~(1 << buffer_index);
+ }
+ state->dirty_mask = 0;
+}
+
+static void evergreen_emit_vs_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
+{
+ evergreen_emit_constant_buffer(rctx, &rctx->vs_constbuf_state, 176,
+ R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
+ R_028980_ALU_CONST_CACHE_VS_0);
+}
+
+static void evergreen_emit_ps_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
+{
+ evergreen_emit_constant_buffer(rctx, &rctx->ps_constbuf_state, 0,
+ R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
+ R_028940_ALU_CONST_CACHE_PS_0);
+}
+
void evergreen_init_state_functions(struct r600_context *rctx)
{
r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 6, 0);
r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
+ r600_init_atom(&rctx->vertex_buffer_state, evergreen_emit_vertex_buffers, 0, 0);
+ r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffer, 0, 0);
+ r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffer, 0, 0);
rctx->context.create_blend_state = evergreen_create_blend_state;
rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
rctx->context.set_viewport_state = evergreen_set_viewport_state;
rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
- rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
rctx->context.texture_barrier = r600_texture_barrier;
rctx->context.create_stream_output_target = r600_create_so_target;
rctx->context.stream_output_target_destroy = r600_so_target_destroy;
offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
r600_pipe_state_add_reg(&state,
R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
- fui(rctx->rasterizer->offset_scale), NULL, 0);
+ fui(rctx->rasterizer->offset_scale));
r600_pipe_state_add_reg(&state,
R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
- fui(offset_units), NULL, 0);
+ fui(offset_units));
r600_pipe_state_add_reg(&state,
R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
- fui(rctx->rasterizer->offset_scale), NULL, 0);
+ fui(rctx->rasterizer->offset_scale));
r600_pipe_state_add_reg(&state,
R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
- fui(offset_units), NULL, 0);
+ fui(offset_units));
r600_pipe_state_add_reg(&state,
R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
- offset_db_fmt_cntl, NULL, 0);
+ offset_db_fmt_cntl);
r600_context_pipe_state_set(rctx, &state);
}
}
}
r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
- tmp, NULL, 0);
+ tmp);
idx++;
}
/* always at least export 1 component per pixel */
exports_ps = 2;
}
-
+ shader->ps_cb_shader_mask = (1ULL << ((unsigned)num_cout * 4)) - 1;
if (ninterp == 0) {
ninterp = 1;
have_perspective = TRUE;
S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
- spi_ps_in_control_0, NULL, 0);
+ spi_ps_in_control_0);
r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
- spi_ps_in_control_1, NULL, 0);
+ spi_ps_in_control_1);
r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
- 0, NULL, 0);
- r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0);
+ 0);
+ r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
r600_pipe_state_add_reg(rstate,
R_0286E0_SPI_BARYC_CNTL,
- spi_baryc_cntl,
- NULL, 0);
+ spi_baryc_cntl);
- r600_pipe_state_add_reg(rstate,
+ r600_pipe_state_add_reg_bo(rstate,
R_028840_SQ_PGM_START_PS,
r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
shader->bo, RADEON_USAGE_READ);
R_028844_SQ_PGM_RESOURCES_PS,
S_028844_NUM_GPRS(rshader->bc.ngpr) |
S_028844_PRIME_CACHE_ON_DRAW(1) |
- S_028844_STACK_SIZE(rshader->bc.nstack),
- NULL, 0);
+ S_028844_STACK_SIZE(rshader->bc.nstack));
r600_pipe_state_add_reg(rstate,
R_02884C_SQ_PGM_EXPORTS_PS,
- exports_ps, NULL, 0);
+ exports_ps);
r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
- db_shader_control,
- NULL, 0);
+ db_shader_control);
shader->sprite_coord_enable = rctx->sprite_coord_enable;
if (rctx->rasterizer)
for (i = 0; i < 10; i++) {
r600_pipe_state_add_reg(rstate,
R_02861C_SPI_VS_OUT_ID_0 + i * 4,
- spi_vs_out_id[i], NULL, 0);
+ spi_vs_out_id[i]);
}
/* Certain attributes (position, psize, etc.) don't count as params.
r600_pipe_state_add_reg(rstate,
R_0286C4_SPI_VS_OUT_CONFIG,
- S_0286C4_VS_EXPORT_COUNT(nparams - 1),
- NULL, 0);
+ S_0286C4_VS_EXPORT_COUNT(nparams - 1));
r600_pipe_state_add_reg(rstate,
R_028860_SQ_PGM_RESOURCES_VS,
S_028860_NUM_GPRS(rshader->bc.ngpr) |
- S_028860_STACK_SIZE(rshader->bc.nstack),
- NULL, 0);
- r600_pipe_state_add_reg(rstate,
+ S_028860_STACK_SIZE(rshader->bc.nstack));
+ r600_pipe_state_add_reg_bo(rstate,
R_02885C_SQ_PGM_START_VS,
r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
shader->bo, RADEON_USAGE_READ);
struct r600_pipe_state *rstate = &ve->rstate;
rstate->id = R600_PIPE_STATE_FETCH_SHADER;
rstate->nregs = 0;
- r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
+ r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
ve->fetch_shader, RADEON_USAGE_READ);
}
R_028000_DB_RENDER_CONTROL,
S_028000_DEPTH_COPY_ENABLE(1) |
S_028000_STENCIL_COPY_ENABLE(1) |
- S_028000_COPY_CENTROID(1),
- NULL, 0);
+ S_028000_COPY_CENTROID(1));
/* Don't set the 'is_flush' flag in r600_pipe_dsa, evergreen doesn't need it. */
return rstate;
}
-
-void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
- struct r600_pipe_resource_state *rstate)
-{
- rstate->id = R600_PIPE_STATE_RESOURCE;
-
- rstate->val[0] = 0;
- rstate->bo[0] = NULL;
- rstate->val[1] = 0;
- rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
- rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
- S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
- S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
- S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
- rstate->val[4] = 0;
- rstate->val[5] = 0;
- rstate->val[6] = 0;
- rstate->val[7] = 0xc0000000;
-}
-
-
-void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
- struct r600_pipe_resource_state *rstate,
- struct r600_resource *rbuffer,
- unsigned offset, unsigned stride,
- enum radeon_bo_usage usage)
-{
- uint64_t va;
-
- va = r600_resource_va(ctx->screen, (void *)rbuffer);
- rstate->bo[0] = rbuffer;
- rstate->bo_usage[0] = usage;
- rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
- rstate->val[1] = rbuffer->buf->size - offset - 1;
- rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
- S_030008_STRIDE(stride) |
- (((va + offset) >> 32UL) & 0xFF);
-}
projects / mesa.git / blobdiff