return 0;
}
-static unsigned r600_tex_dim(unsigned dim)
+static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
{
switch (dim) {
default:
return V_030000_SQ_TEX_DIM_1D_ARRAY;
case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_RECT:
- return V_030000_SQ_TEX_DIM_2D;
+ return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
+ V_030000_SQ_TEX_DIM_2D;
case PIPE_TEXTURE_2D_ARRAY:
- return V_030000_SQ_TEX_DIM_2D_ARRAY;
+ return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
+ V_030000_SQ_TEX_DIM_2D_ARRAY;
case PIPE_TEXTURE_3D:
return V_030000_SQ_TEX_DIM_3D;
case PIPE_TEXTURE_CUBE:
unsigned sample_count,
unsigned usage)
{
+ struct r600_screen *rscreen = (struct r600_screen*)screen;
unsigned retval = 0;
if (target >= PIPE_MAX_TEXTURE_TYPES) {
if (!util_format_is_supported(format, usage))
return FALSE;
- /* Multisample */
- if (sample_count > 1)
- return FALSE;
+ if (sample_count > 1) {
+ if (rscreen->info.drm_minor < 19)
+ return FALSE;
+
+ if (rscreen->chip_class != EVERGREEN)
+ return FALSE;
+
+ switch (sample_count) {
+ case 2:
+ case 4:
+ case 8:
+ break;
+ default:
+ return FALSE;
+ }
+
+ /* require render-target support for multisample resources */
+ if (util_format_is_depth_or_stencil(format)) {
+ usage |= PIPE_BIND_DEPTH_STENCIL;
+ } else {
+ usage |= PIPE_BIND_RENDER_TARGET;
+ }
+ }
if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
r600_is_sampler_format_supported(screen, format)) {
return retval == usage;
}
-static void *evergreen_create_blend_state(struct pipe_context *ctx,
- const struct pipe_blend_state *state)
+static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
+ const struct pipe_blend_state *state, int mode)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
blend->cb_target_mask = target_mask;
if (target_mask)
- color_control |= S_028808_MODE(V_028808_CB_NORMAL);
+ color_control |= S_028808_MODE(mode);
else
color_control |= S_028808_MODE(V_028808_CB_DISABLE);
r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
}
+ r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK,
+ S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
+ S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
+ S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
+ S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
+ S_028B70_ALPHA_TO_MASK_OFFSET3(2));
+
blend->alpha_to_one = state->alpha_to_one;
return rstate;
}
+static void *evergreen_create_blend_state(struct pipe_context *ctx,
+ const struct pipe_blend_state *state)
+{
+
+ return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
+}
+
static void *evergreen_create_dsa_state(struct pipe_context *ctx,
const struct pipe_depth_stencil_alpha_state *state)
{
tmp = (unsigned)state->line_width * 8;
r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
+ S_028A48_MSAA_ENABLE(state->multisample) |
S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
{
struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
- struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
+ struct r600_texture *tmp = (struct r600_texture*)texture;
unsigned format, endian;
uint32_t word4 = 0, yuv_format = 0, pitch = 0;
unsigned char swizzle[4], array_mode = 0, tile_type = 0;
}
view->tex_resource = &tmp->resource;
- view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
+ view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
S_030000_PITCH((pitch / 8) - 1) |
S_030000_TEX_WIDTH(width - 1));
if (rscreen->chip_class == CAYMAN)
view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
S_030004_TEX_DEPTH(depth - 1) |
S_030004_ARRAY_MODE(array_mode));
- view->tex_resource_words[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
- if (state->u.tex.last_level) {
- view->tex_resource_words[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
+ view->tex_resource_words[2] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
+ if (state->u.tex.last_level && texture->nr_samples <= 1) {
+ view->tex_resource_words[3] = (tmp->surface.level[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
} else {
- view->tex_resource_words[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
+ view->tex_resource_words[3] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
}
view->tex_resource_words[4] = (word4 |
S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
- S_030010_ENDIAN_SWAP(endian) |
- S_030010_BASE_LEVEL(state->u.tex.first_level));
- view->tex_resource_words[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
- S_030014_BASE_ARRAY(state->u.tex.first_layer) |
- S_030014_LAST_ARRAY(state->u.tex.last_layer));
+ S_030010_ENDIAN_SWAP(endian));
+ view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
+ S_030014_LAST_ARRAY(state->u.tex.last_layer);
+ if (texture->nr_samples > 1) {
+ /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
+ view->tex_resource_words[5] |= S_030014_LAST_LEVEL(util_logbase2(texture->nr_samples));
+ } else {
+ view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
+ view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
+ }
/* aniso max 16 samples */
view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
(S_030018_TILE_SPLIT(tile_split));
static void evergreen_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
struct pipe_sampler_view **views)
{
- struct r600_context *rctx = (struct r600_context *)ctx;
- r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views);
+ r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
}
static void evergreen_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
struct pipe_sampler_view **views)
{
- struct r600_context *rctx = (struct r600_context *)ctx;
- r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views);
+ r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
}
static void evergreen_set_clip_state(struct pipe_context *ctx,
{
}
-static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
-{
-}
-
static void evergreen_get_scissor_rect(struct r600_context *rctx,
unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
uint32_t *tl, uint32_t *br)
struct r600_surface *surf)
{
struct r600_screen *rscreen = rctx->screen;
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
+ struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
struct pipe_resource *pipe_tex = surf->base.texture;
unsigned level = surf->base.u.tex.level;
unsigned pitch, slice;
{
struct r600_screen *rscreen = rctx->screen;
struct pipe_screen *screen = &rscreen->screen;
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
+ struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
uint64_t offset;
unsigned level, pitch, slice, format, array_mode;
unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
surf->depth_initialized = true;
}
+#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
+ (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
+ (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
+ (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
+ (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
+
+static uint32_t evergreen_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
+{
+ /* 2xMSAA
+ * There are two locations (-4, 4), (4, -4). */
+ static uint32_t sample_locs_2x[] = {
+ FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
+ FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
+ FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
+ FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
+ };
+ static unsigned max_dist_2x = 4;
+ /* 4xMSAA
+ * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
+ static uint32_t sample_locs_4x[] = {
+ FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
+ FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
+ FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
+ FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
+ };
+ static unsigned max_dist_4x = 6;
+ /* 8xMSAA */
+ static uint32_t eg_sample_locs_8x[] = {
+ FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
+ FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
+ FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
+ FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
+ FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
+ FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
+ FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
+ FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
+ };
+ static uint32_t cm_sample_locs_8x[] = {
+ FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
+ FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
+ FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
+ FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
+ FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
+ FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
+ FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
+ FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
+ };
+ static unsigned max_dist_8x = 8;
+ /* 16xMSAA */
+ static uint32_t cm_sample_locs_16x[] = {
+ FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
+ FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
+ FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
+ FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
+ FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
+ FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
+ FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
+ FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
+ FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
+ FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
+ FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
+ FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
+ FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
+ FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
+ FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
+ FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
+ };
+ static unsigned max_dist_16x = 8;
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ uint32_t max_dist, num_regs, *sample_locs, i;
+
+ switch (nsample) {
+ case 2:
+ sample_locs = sample_locs_2x;
+ num_regs = Elements(sample_locs_2x);
+ max_dist = max_dist_2x;
+ break;
+ case 4:
+ sample_locs = sample_locs_4x;
+ num_regs = Elements(sample_locs_4x);
+ max_dist = max_dist_4x;
+ break;
+ case 8:
+ if (rctx->chip_class == CAYMAN) {
+ sample_locs = cm_sample_locs_8x;
+ num_regs = Elements(cm_sample_locs_8x);
+ } else {
+ sample_locs = eg_sample_locs_8x;
+ num_regs = Elements(eg_sample_locs_8x);
+ }
+ max_dist = max_dist_8x;
+ break;
+ case 16:
+ if (rctx->chip_class == CAYMAN) {
+ sample_locs = cm_sample_locs_16x;
+ num_regs = Elements(cm_sample_locs_16x);
+ max_dist = max_dist_16x;
+ break;
+ }
+ /* fall through */
+ default:
+ R600_ERR("Invalid nr_samples %i\n", nsample);
+ return 0;
+ }
+
+ /* All the regs must be initialized. Otherwise weird rendering may occur. */
+ if (rctx->chip_class == CAYMAN) {
+ r600_pipe_state_add_reg(rstate, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs[0]);
+ r600_pipe_state_add_reg(rstate, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs[1]);
+ r600_pipe_state_add_reg(rstate, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs[2]);
+ r600_pipe_state_add_reg(rstate, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs[3]);
+ if (num_regs <= 8) {
+ r600_pipe_state_add_reg(rstate, CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs[4]);
+ r600_pipe_state_add_reg(rstate, CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs[5]);
+ r600_pipe_state_add_reg(rstate, CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs[6]);
+ r600_pipe_state_add_reg(rstate, CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs[7]);
+ }
+ if (num_regs <= 16) {
+ r600_pipe_state_add_reg(rstate, CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, sample_locs[8]);
+ r600_pipe_state_add_reg(rstate, CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, sample_locs[9]);
+ r600_pipe_state_add_reg(rstate, CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, sample_locs[10]);
+ r600_pipe_state_add_reg(rstate, CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, sample_locs[11]);
+ r600_pipe_state_add_reg(rstate, CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, sample_locs[12]);
+ r600_pipe_state_add_reg(rstate, CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, sample_locs[13]);
+ r600_pipe_state_add_reg(rstate, CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, sample_locs[14]);
+ r600_pipe_state_add_reg(rstate, CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, sample_locs[15]);
+ }
+ } else {
+ for (i = 0; i < num_regs; i++) {
+ r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
+ sample_locs[i]);
+ }
+ }
+ return max_dist;
+}
+
static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
const struct pipe_framebuffer_state *state)
{
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
struct r600_surface *surf;
struct r600_resource *res;
- uint32_t tl, br;
- int i;
+ uint32_t tl, br, i, nr_samples;
if (rstate == NULL)
return;
util_copy_framebuffer_state(&rctx->framebuffer, state);
- /* build states */
+ /* Colorbuffers. */
rctx->export_16bpc = true;
rctx->nr_cbufs = state->nr_cbufs;
rctx->cb0_is_integer = state->nr_cbufs &&
surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
}
/* set CB_COLOR1_INFO for possible dual-src blending */
- if (i == 1 && !((struct r600_resource_texture*)res)->is_rat) {
+ if (i == 1 && !((struct r600_texture*)res)->is_rat) {
r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
surf->cb_color_info, res, RADEON_USAGE_READWRITE);
i++;
}
}
+ /* ZS buffer. */
if (state->zsbuf) {
surf = (struct r600_surface*)state->zsbuf;
res = (struct r600_resource*)surf->base.texture;
r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice);
}
+ /* Framebuffer dimensions. */
evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
r600_pipe_state_add_reg(rstate,
r600_pipe_state_add_reg(rstate,
R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
+ /* Multisampling */
+ if (state->nr_cbufs)
+ nr_samples = state->cbufs[0]->texture->nr_samples;
+ else if (state->zsbuf)
+ nr_samples = state->zsbuf->texture->nr_samples;
+ else
+ nr_samples = 0;
+
+ if (nr_samples > 1) {
+ unsigned log_samples = util_logbase2(nr_samples);
+ unsigned max_dist, line_cntl, aa_config;
+
+ max_dist = evergreen_set_ms_pos(ctx, rstate, nr_samples);
+
+ line_cntl = S_028C00_LAST_PIXEL(1) |
+ S_028C00_EXPAND_LINE_WIDTH(1);
+ aa_config = S_028C04_MSAA_NUM_SAMPLES(log_samples) |
+ S_028C04_MAX_SAMPLE_DIST(max_dist);
+
+ if (rctx->chip_class == CAYMAN) {
+ r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, line_cntl);
+ r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG, aa_config);
+ } else {
+ r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, line_cntl);
+ r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, aa_config);
+ }
+ } else {
+ if (rctx->chip_class == CAYMAN) {
+ r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
+ r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG, 0);
+ } else {
+ r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
+ r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
+ }
+ }
+
free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
r600_context_pipe_state_set(rctx, rstate);
db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
- S_028000_COPY_CENTROID(1);
+ S_028000_COPY_CENTROID(1) |
+ S_028000_COPY_SAMPLE(a->copy_sample);
}
r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
evergreen_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
}
+static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
+{
+ struct r600_sample_mask *s = (struct r600_sample_mask*)a;
+ uint8_t mask = s->sample_mask;
+
+ r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
+ mask | (mask << 8) | (mask << 16) | (mask << 24));
+}
+
+static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
+{
+ struct r600_sample_mask *s = (struct r600_sample_mask*)a;
+ struct radeon_winsys_cs *cs = rctx->cs;
+ uint16_t mask = s->sample_mask;
+
+ r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
+ r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
+ r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
+}
+
void evergreen_init_state_functions(struct r600_context *rctx)
{
r600_init_atom(&rctx->cb_misc_state.atom, evergreen_emit_cb_misc_state, 0, 0);
r600_init_atom(&rctx->vs_samplers.atom_sampler, evergreen_emit_vs_sampler, 0, 0);
r600_init_atom(&rctx->ps_samplers.atom_sampler, evergreen_emit_ps_sampler, 0, 0);
+ if (rctx->chip_class == EVERGREEN)
+ r600_init_atom(&rctx->sample_mask.atom, evergreen_emit_sample_mask, 3, 0);
+ else
+ r600_init_atom(&rctx->sample_mask.atom, cayman_emit_sample_mask, 4, 0);
+ rctx->sample_mask.sample_mask = ~0;
+ r600_atom_dirty(rctx, &rctx->sample_mask.atom);
+
rctx->context.create_blend_state = evergreen_create_blend_state;
rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
rctx->context.create_fs_state = r600_create_shader_state_ps;
rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_views;
rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
- rctx->context.set_sample_mask = evergreen_set_sample_mask;
+ rctx->context.set_sample_mask = r600_set_sample_mask;
rctx->context.set_scissor_state = evergreen_set_scissor_state;
rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
- r600_store_context_reg_seq(cb, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
- r600_store_value(cb, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
- r600_store_value(cb, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
-
r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
- r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
-
- r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
- r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
- r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
- r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
-
- r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
- r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
- r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
-
- r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
+ r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
- r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
-
- r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0);
r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
ve->fetch_shader, RADEON_USAGE_READ);
}
+void *evergreen_create_resolve_blend(struct r600_context *rctx)
+{
+ struct pipe_blend_state blend;
+ struct r600_pipe_state *rstate;
+
+ memset(&blend, 0, sizeof(blend));
+ blend.rt[0].colormask = 0xf;
+ rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
+ return rstate;
+}
+
void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
{
struct pipe_depth_stencil_alpha_state dsa = {{0}};
unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
- S_02880C_DB_SOURCE_FORMAT(db_source_format);
+ S_02880C_DB_SOURCE_FORMAT(db_source_format) |
+ S_02880C_ALPHA_TO_MASK_DISABLE(rctx->cb0_is_integer);
if (db_shader_control != rctx->db_shader_control) {
struct r600_pipe_state rstate;
projects / mesa.git / blobdiff