r600g: make F2U trans-only on r600-r700

[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index c80e330a5b82f0ee8ec3c789a8395bc5f2e4831d..8ec1a91893570d6e9213e80836ad0f04cec04eda 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -993,7 +993,7 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 {
        struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
        struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
-       struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
+       struct r600_texture *tmp = (struct r600_texture*)texture;
        unsigned format, endian;
        uint32_t word4 = 0, yuv_format = 0, pitch = 0;
        unsigned char swizzle[4], array_mode = 0, tile_type = 0;
@@ -1090,11 +1090,11 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
        view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
                                       S_030004_TEX_DEPTH(depth - 1) |
                                       S_030004_ARRAY_MODE(array_mode));
-       view->tex_resource_words[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
+       view->tex_resource_words[2] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
        if (state->u.tex.last_level && texture->nr_samples <= 1) {
-               view->tex_resource_words[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
+               view->tex_resource_words[3] = (tmp->surface.level[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
        } else {
-               view->tex_resource_words[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
+               view->tex_resource_words[3] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
        }
        view->tex_resource_words[4] = (word4 |
                                       S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
@@ -1244,7 +1244,7 @@ void evergreen_init_color_surface(struct r600_context *rctx,
                                  struct r600_surface *surf)
 {
        struct r600_screen *rscreen = rctx->screen;
-       struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
+       struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
        struct pipe_resource *pipe_tex = surf->base.texture;
        unsigned level = surf->base.u.tex.level;
        unsigned pitch, slice;
@@ -1418,7 +1418,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
 {
        struct r600_screen *rscreen = rctx->screen;
        struct pipe_screen *screen = &rscreen->screen;
-       struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
+       struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
        uint64_t offset;
        unsigned level, pitch, slice, format, array_mode;
        unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
@@ -1677,7 +1677,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
                                           surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
        }
        /* set CB_COLOR1_INFO for possible dual-src blending */
-       if (i == 1 && !((struct r600_resource_texture*)res)->is_rat) {
+       if (i == 1 && !((struct r600_texture*)res)->is_rat) {
                r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
                                           surf->cb_color_info, res, RADEON_USAGE_READWRITE);
                i++;