static inline unsigned evergreen_array_mode(unsigned mode)
{
switch (mode) {
+ default:
case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
break;
case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
break;
case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
- default:
- case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL;
}
}
static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
{
- return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
+ return r600_translate_texformat(screen, format, NULL, NULL, NULL,
+ FALSE) != ~0U;
}
static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
{
- return r600_translate_colorformat(chip, format) != ~0U &&
- r600_translate_colorswap(format) != ~0U;
+ return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
+ r600_translate_colorswap(format, FALSE) != ~0U;
}
static bool r600_is_zs_format_supported(enum pipe_format format)
retval |= PIPE_BIND_VERTEX_BUFFER;
}
- if (usage & PIPE_BIND_TRANSFER_READ)
- retval |= PIPE_BIND_TRANSFER_READ;
- if (usage & PIPE_BIND_TRANSFER_WRITE)
- retval |= PIPE_BIND_TRANSFER_WRITE;
+ if ((usage & PIPE_BIND_LINEAR) &&
+ !util_format_is_compressed(format) &&
+ !(usage & PIPE_BIND_DEPTH_STENCIL))
+ retval |= PIPE_BIND_LINEAR;
return retval == usage;
}
r600_init_command_buffer(&rs->buffer, 30);
+ rs->scissor_enable = state->scissor;
+ rs->clip_halfz = state->clip_halfz;
rs->flatshade = state->flatshade;
rs->sprite_coord_enable = state->sprite_coord_enable;
+ rs->rasterizer_discard = state->rasterizer_discard;
rs->two_side = state->light_twoside;
rs->clip_plane_enable = state->clip_plane_enable;
rs->pa_sc_line_stipple = state->line_stipple_enable ?
S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
rs->pa_cl_clip_cntl =
- S_028810_PS_UCP_MODE(3) |
S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
rs->offset_units = state->offset_units;
rs->offset_scale = state->offset_scale * 16.0f;
rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
+ rs->offset_units_unscaled = state->offset_units_unscaled;
if (state->point_size_per_vertex) {
psize_min = util_get_min_point_size(state);
r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
S_028A48_MSAA_ENABLE(state->multisample) |
- S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
+ S_028A48_VPORT_SCISSOR_ENABLE(1) |
S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
if (rctx->b.chip_class == CAYMAN) {
static void *evergreen_create_sampler_state(struct pipe_context *ctx,
const struct pipe_sampler_state *state)
{
+ struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
- unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
+ unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
+ : state->max_anisotropy;
+ unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
if (!ss) {
return NULL;
S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
- S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
- S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
+ S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
+ S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
- S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
+ S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
/* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
return ss;
}
-static struct pipe_sampler_view *
-texture_buffer_sampler_view(struct r600_context *rctx,
- struct r600_pipe_sampler_view *view,
- unsigned width0, unsigned height0)
-
+struct eg_buf_res_params {
+ enum pipe_format pipe_format;
+ unsigned offset;
+ unsigned size;
+ unsigned char swizzle[4];
+ bool uncached;
+};
+
+static void evergreen_fill_buffer_resource_words(struct r600_context *rctx,
+ struct pipe_resource *buffer,
+ struct eg_buf_res_params *params,
+ bool *skip_mip_address_reloc,
+ unsigned tex_resource_words[8])
{
- struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
+ struct r600_texture *tmp = (struct r600_texture*)buffer;
uint64_t va;
- int stride = util_format_get_blocksize(view->base.format);
+ int stride = util_format_get_blocksize(params->pipe_format);
unsigned format, num_format, format_comp, endian;
unsigned swizzle_res;
- unsigned char swizzle[4];
const struct util_format_description *desc;
- unsigned offset = view->base.u.buf.first_element * stride;
- unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
-
- swizzle[0] = view->base.swizzle_r;
- swizzle[1] = view->base.swizzle_g;
- swizzle[2] = view->base.swizzle_b;
- swizzle[3] = view->base.swizzle_a;
- r600_vertex_data_type(view->base.format,
+ r600_vertex_data_type(params->pipe_format,
&format, &num_format, &format_comp,
&endian);
- desc = util_format_description(view->base.format);
+ desc = util_format_description(params->pipe_format);
- swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
+ swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, TRUE);
- va = tmp->resource.gpu_address + offset;
- view->tex_resource = &tmp->resource;
-
- view->skip_mip_address_reloc = true;
- view->tex_resource_words[0] = va;
- view->tex_resource_words[1] = size - 1;
- view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
+ va = tmp->resource.gpu_address + params->offset;
+ *skip_mip_address_reloc = true;
+ tex_resource_words[0] = va;
+ tex_resource_words[1] = params->size - 1;
+ tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
S_030008_STRIDE(stride) |
S_030008_DATA_FORMAT(format) |
S_030008_NUM_FORMAT_ALL(num_format) |
S_030008_FORMAT_COMP_ALL(format_comp) |
S_030008_ENDIAN_SWAP(endian);
- view->tex_resource_words[3] = swizzle_res;
+ tex_resource_words[3] = swizzle_res | S_03000C_UNCACHED(params->uncached);
/*
* in theory dword 4 is for number of elements, for use with resinfo,
* but it seems to utterly fail to work, the amd gpu shader analyser
* uses a const buffer to store the element sizes for buffer txq
*/
- view->tex_resource_words[4] = 0;
- view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
- view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
+ tex_resource_words[4] = 0;
+ tex_resource_words[5] = tex_resource_words[6] = 0;
+ tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
+}
+
+static struct pipe_sampler_view *
+texture_buffer_sampler_view(struct r600_context *rctx,
+ struct r600_pipe_sampler_view *view,
+ unsigned width0, unsigned height0)
+{
+ struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
+ struct eg_buf_res_params params;
+
+ memset(¶ms, 0, sizeof(params));
+
+ params.pipe_format = view->base.format;
+ params.offset = view->base.u.buf.offset;
+ params.size = view->base.u.buf.size;
+ params.swizzle[0] = view->base.swizzle_r;
+ params.swizzle[1] = view->base.swizzle_g;
+ params.swizzle[2] = view->base.swizzle_b;
+ params.swizzle[3] = view->base.swizzle_a;
+
+ evergreen_fill_buffer_resource_words(rctx, view->base.texture,
+ ¶ms, &view->skip_mip_address_reloc,
+ view->tex_resource_words);
+ view->tex_resource = &tmp->resource;
if (tmp->resource.gpu_address)
- LIST_ADDTAIL(&view->list, &rctx->b.texture_buffers);
+ LIST_ADDTAIL(&view->list, &rctx->texture_buffers);
return &view->base;
}
-struct pipe_sampler_view *
-evergreen_create_sampler_view_custom(struct pipe_context *ctx,
- struct pipe_resource *texture,
- const struct pipe_sampler_view *state,
- unsigned width0, unsigned height0,
- unsigned force_level)
+struct eg_tex_res_params {
+ enum pipe_format pipe_format;
+ int force_level;
+ unsigned width0;
+ unsigned height0;
+ unsigned first_level;
+ unsigned last_level;
+ unsigned first_layer;
+ unsigned last_layer;
+ unsigned target;
+ unsigned char swizzle[4];
+};
+
+static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
+ struct pipe_resource *texture,
+ struct eg_tex_res_params *params,
+ bool *skip_mip_address_reloc,
+ unsigned tex_resource_words[8])
{
- struct r600_context *rctx = (struct r600_context*)ctx;
- struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
- struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
+ struct r600_screen *rscreen = (struct r600_screen*)rctx->b.b.screen;
struct r600_texture *tmp = (struct r600_texture*)texture;
unsigned format, endian;
uint32_t word4 = 0, yuv_format = 0, pitch = 0;
- unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
+ unsigned char array_mode = 0, non_disp_tiling = 0;
unsigned height, depth, width;
unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
- enum pipe_format pipe_format = state->format;
- struct radeon_surf_level *surflevel;
+ struct legacy_surf_level *surflevel;
unsigned base_level, first_level, last_level;
unsigned dim, last_layer;
uint64_t va;
+ bool do_endian_swap = FALSE;
- if (!view)
- return NULL;
-
- /* initialize base object */
- view->base = *state;
- view->base.texture = NULL;
- pipe_reference(NULL, &texture->reference);
- view->base.texture = texture;
- view->base.reference.count = 1;
- view->base.context = ctx;
-
- if (state->target == PIPE_BUFFER)
- return texture_buffer_sampler_view(rctx, view, width0, height0);
-
- swizzle[0] = state->swizzle_r;
- swizzle[1] = state->swizzle_g;
- swizzle[2] = state->swizzle_b;
- swizzle[3] = state->swizzle_a;
-
- tile_split = tmp->surface.tile_split;
- surflevel = tmp->surface.level;
+ tile_split = tmp->surface.u.legacy.tile_split;
+ surflevel = tmp->surface.u.legacy.level;
/* Texturing with separate depth and stencil. */
- if (tmp->is_depth && !tmp->is_flushing_texture) {
- switch (pipe_format) {
+ if (tmp->db_compatible) {
+ switch (params->pipe_format) {
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- pipe_format = PIPE_FORMAT_Z32_FLOAT;
+ params->pipe_format = PIPE_FORMAT_Z32_FLOAT;
break;
case PIPE_FORMAT_X8Z24_UNORM:
case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- /* Z24 is always stored like this. */
- pipe_format = PIPE_FORMAT_Z24X8_UNORM;
+ /* Z24 is always stored like this for DB
+ * compatibility.
+ */
+ params->pipe_format = PIPE_FORMAT_Z24X8_UNORM;
break;
case PIPE_FORMAT_X24S8_UINT:
case PIPE_FORMAT_S8X24_UINT:
case PIPE_FORMAT_X32_S8X24_UINT:
- pipe_format = PIPE_FORMAT_S8_UINT;
- tile_split = tmp->surface.stencil_tile_split;
- surflevel = tmp->surface.stencil_level;
+ params->pipe_format = PIPE_FORMAT_S8_UINT;
+ tile_split = tmp->surface.u.legacy.stencil_tile_split;
+ surflevel = tmp->surface.u.legacy.stencil_level;
break;
default:;
}
}
- format = r600_translate_texformat(ctx->screen, pipe_format,
- swizzle,
- &word4, &yuv_format);
+ if (R600_BIG_ENDIAN)
+ do_endian_swap = !tmp->db_compatible;
+
+ format = r600_translate_texformat(rctx->b.b.screen, params->pipe_format,
+ params->swizzle,
+ &word4, &yuv_format, do_endian_swap);
assert(format != ~0);
if (format == ~0) {
- FREE(view);
- return NULL;
+ return -1;
}
- endian = r600_colorformat_endian_swap(format);
+ endian = r600_colorformat_endian_swap(format, do_endian_swap);
base_level = 0;
- first_level = state->u.tex.first_level;
- last_level = state->u.tex.last_level;
- width = width0;
- height = height0;
+ first_level = params->first_level;
+ last_level = params->last_level;
+ width = params->width0;
+ height = params->height0;
depth = texture->depth0;
- if (force_level) {
- base_level = force_level;
+ if (params->force_level) {
+ base_level = params->force_level;
first_level = 0;
last_level = 0;
- width = u_minify(width, force_level);
- height = u_minify(height, force_level);
- depth = u_minify(depth, force_level);
+ width = u_minify(width, params->force_level);
+ height = u_minify(height, params->force_level);
+ depth = u_minify(depth, params->force_level);
}
- pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
+ pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(params->pipe_format);
non_disp_tiling = tmp->non_disp_tiling;
switch (surflevel[base_level].mode) {
+ default:
case RADEON_SURF_MODE_LINEAR_ALIGNED:
array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
break;
case RADEON_SURF_MODE_1D:
array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
break;
- case RADEON_SURF_MODE_LINEAR:
- default:
- array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
- break;
}
- macro_aspect = tmp->surface.mtilea;
- bankw = tmp->surface.bankw;
- bankh = tmp->surface.bankh;
+ macro_aspect = tmp->surface.u.legacy.mtilea;
+ bankw = tmp->surface.u.legacy.bankw;
+ bankh = tmp->surface.u.legacy.bankh;
tile_split = eg_tile_split(tile_split);
macro_aspect = eg_macro_tile_aspect(macro_aspect);
bankw = eg_bank_wh(bankw);
/* 128 bit formats require tile type = 1 */
if (rscreen->b.chip_class == CAYMAN) {
- if (util_format_get_blocksize(pipe_format) >= 16)
+ if (util_format_get_blocksize(params->pipe_format) >= 16)
non_disp_tiling = 1;
}
- nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
+ nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
- if (state->target == PIPE_TEXTURE_1D_ARRAY) {
+ if (params->target == PIPE_TEXTURE_1D_ARRAY) {
height = 1;
depth = texture->array_size;
- } else if (state->target == PIPE_TEXTURE_2D_ARRAY) {
+ } else if (params->target == PIPE_TEXTURE_2D_ARRAY) {
depth = texture->array_size;
- } else if (state->target == PIPE_TEXTURE_CUBE_ARRAY)
+ } else if (params->target == PIPE_TEXTURE_CUBE_ARRAY)
depth = texture->array_size / 6;
va = tmp->resource.gpu_address;
- if (state->format == PIPE_FORMAT_X24S8_UINT ||
- state->format == PIPE_FORMAT_S8X24_UINT ||
- state->format == PIPE_FORMAT_X32_S8X24_UINT ||
- state->format == PIPE_FORMAT_S8_UINT)
- view->is_stencil_sampler = true;
-
- view->tex_resource = &tmp->resource;
-
/* array type views and views into array types need to use layer offset */
- dim = state->target;
- if (state->target != PIPE_TEXTURE_CUBE)
- dim = MAX2(state->target, texture->target);
+ dim = params->target;
+ if (params->target != PIPE_TEXTURE_CUBE)
+ dim = MAX2(params->target, texture->target);
- view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(dim, texture->nr_samples)) |
+ tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(dim, texture->nr_samples)) |
S_030000_PITCH((pitch / 8) - 1) |
S_030000_TEX_WIDTH(width - 1));
if (rscreen->b.chip_class == CAYMAN)
- view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
+ tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
else
- view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
- view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
+ tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
+ tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
S_030004_TEX_DEPTH(depth - 1) |
S_030004_ARRAY_MODE(array_mode));
- view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
+ tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
+ *skip_mip_address_reloc = false;
/* TEX_RESOURCE_WORD3.MIP_ADDRESS */
if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
if (tmp->is_depth) {
/* disable FMASK (0 = disabled) */
- view->tex_resource_words[3] = 0;
- view->skip_mip_address_reloc = true;
+ tex_resource_words[3] = 0;
+ *skip_mip_address_reloc = true;
} else {
/* FMASK should be in MIP_ADDRESS for multisample textures */
- view->tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
+ tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
}
} else if (last_level && texture->nr_samples <= 1) {
- view->tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
+ tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
} else {
- view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
+ tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
}
- last_layer = state->u.tex.last_layer;
- if (state->target != texture->target && depth == 1) {
- last_layer = state->u.tex.first_layer;
+ last_layer = params->last_layer;
+ if (params->target != texture->target && depth == 1) {
+ last_layer = params->first_layer;
}
- view->tex_resource_words[4] = (word4 |
- S_030010_ENDIAN_SWAP(endian));
- view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
- S_030014_LAST_ARRAY(last_layer);
- view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
+ tex_resource_words[4] = (word4 |
+ S_030010_ENDIAN_SWAP(endian));
+ tex_resource_words[5] = S_030014_BASE_ARRAY(params->first_layer) |
+ S_030014_LAST_ARRAY(last_layer);
+ tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
if (texture->nr_samples > 1) {
unsigned log_samples = util_logbase2(texture->nr_samples);
if (rscreen->b.chip_class == CAYMAN) {
- view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
+ tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
}
/* LAST_LEVEL holds log2(nr_samples) for multisample textures */
- view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
- view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
+ tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
+ tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
} else {
- view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
- view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
+ bool no_mip = first_level == last_level;
+
+ tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
+ tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
/* aniso max 16 samples */
- view->tex_resource_words[6] |= S_030018_MAX_ANISO(4);
+ tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
}
- view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
+ tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
S_03001C_BANK_WIDTH(bankw) |
S_03001C_BANK_HEIGHT(bankh) |
S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
S_03001C_NUM_BANKS(nbanks) |
- S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
+ S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
+ return 0;
+}
+
+struct pipe_sampler_view *
+evergreen_create_sampler_view_custom(struct pipe_context *ctx,
+ struct pipe_resource *texture,
+ const struct pipe_sampler_view *state,
+ unsigned width0, unsigned height0,
+ unsigned force_level)
+{
+ struct r600_context *rctx = (struct r600_context*)ctx;
+ struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
+ struct r600_texture *tmp = (struct r600_texture*)texture;
+ struct eg_tex_res_params params;
+ int ret;
+
+ if (!view)
+ return NULL;
+
+ /* initialize base object */
+ view->base = *state;
+ view->base.texture = NULL;
+ pipe_reference(NULL, &texture->reference);
+ view->base.texture = texture;
+ view->base.reference.count = 1;
+ view->base.context = ctx;
+
+ if (state->target == PIPE_BUFFER)
+ return texture_buffer_sampler_view(rctx, view, width0, height0);
+
+ memset(¶ms, 0, sizeof(params));
+ params.pipe_format = state->format;
+ params.force_level = force_level;
+ params.width0 = width0;
+ params.height0 = height0;
+ params.first_level = state->u.tex.first_level;
+ params.last_level = state->u.tex.last_level;
+ params.first_layer = state->u.tex.first_layer;
+ params.last_layer = state->u.tex.last_layer;
+ params.target = state->target;
+ params.swizzle[0] = state->swizzle_r;
+ params.swizzle[1] = state->swizzle_g;
+ params.swizzle[2] = state->swizzle_b;
+ params.swizzle[3] = state->swizzle_a;
+
+ ret = evergreen_fill_tex_resource_words(rctx, texture, ¶ms,
+ &view->skip_mip_address_reloc,
+ view->tex_resource_words);
+ if (ret != 0) {
+ FREE(view);
+ return NULL;
+ }
+
+ if (state->format == PIPE_FORMAT_X24S8_UINT ||
+ state->format == PIPE_FORMAT_S8X24_UINT ||
+ state->format == PIPE_FORMAT_X32_S8X24_UINT ||
+ state->format == PIPE_FORMAT_S8_UINT)
+ view->is_stencil_sampler = true;
+
+ view->tex_resource = &tmp->resource;
+
return &view->base;
}
unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
uint32_t *tl, uint32_t *br)
{
- /* EG hw workaround */
- if (br_x == 0)
- tl_x = 1;
- if (br_y == 0)
- tl_y = 1;
+ struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
- /* cayman hw workaround */
- if (rctx->b.chip_class == CAYMAN) {
- if (br_x == 1 && br_y == 1)
- br_x = 2;
- }
+ evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
- *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
- *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
+ *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
+ *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
}
-static void evergreen_set_scissor_states(struct pipe_context *ctx,
- unsigned start_slot,
- unsigned num_scissors,
- const struct pipe_scissor_state *state)
+struct r600_tex_color_info {
+ unsigned info;
+ unsigned view;
+ unsigned dim;
+ unsigned pitch;
+ unsigned slice;
+ unsigned attrib;
+ unsigned ntype;
+ unsigned fmask;
+ unsigned fmask_slice;
+ uint64_t offset;
+ boolean export_16bpc;
+};
+
+static void evergreen_set_color_surface_buffer(struct r600_context *rctx,
+ struct r600_resource *res,
+ enum pipe_format pformat,
+ unsigned first_element,
+ unsigned last_element,
+ struct r600_tex_color_info *color)
{
- struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_scissor_state *rstate = &rctx->scissor;
+ unsigned format, swap, ntype, endian;
+ const struct util_format_description *desc;
+ unsigned block_size = align(util_format_get_blocksize(res->b.b.format), 4);
+ unsigned pitch_alignment =
+ MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
+ unsigned pitch = align(res->b.b.width0, pitch_alignment);
int i;
+ unsigned width_elements;
- for (i = start_slot; i < start_slot + num_scissors; i++)
- rstate->scissor[i] = state[i - start_slot];
- rstate->dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
- rstate->atom.num_dw = util_bitcount(rstate->dirty_mask) * 4;
- r600_mark_atom_dirty(rctx, &rstate->atom);
-}
+ width_elements = last_element - first_element + 1;
-static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
-{
- struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
- struct r600_scissor_state *rstate = &rctx->scissor;
- struct pipe_scissor_state *state;
- uint32_t dirty_mask;
- unsigned i, offset;
- uint32_t tl, br;
+ format = r600_translate_colorformat(rctx->b.chip_class, pformat, FALSE);
+ swap = r600_translate_colorswap(pformat, FALSE);
- dirty_mask = rstate->dirty_mask;
- while (dirty_mask != 0) {
- i = u_bit_scan(&dirty_mask);
- state = &rstate->scissor[i];
- evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
+ endian = r600_colorformat_endian_swap(format, FALSE);
- offset = i * 4 * 2;
- radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
- radeon_emit(cs, tl);
- radeon_emit(cs, br);
+ desc = util_format_description(pformat);
+ for (i = 0; i < 4; i++) {
+ if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
+ break;
+ }
}
- rstate->dirty_mask = 0;
- rstate->atom.num_dw = 0;
-}
-
-/**
- * This function intializes the CB* register values for RATs. It is meant
- * to be used for 1D aligned buffers that do not have an associated
- * radeon_surf.
- */
-void evergreen_init_color_surface_rat(struct r600_context *rctx,
- struct r600_surface *surf)
-{
- struct pipe_resource *pipe_buffer = surf->base.texture;
- unsigned format = r600_translate_colorformat(rctx->b.chip_class,
- surf->base.format);
- unsigned endian = r600_colorformat_endian_swap(format);
- unsigned swap = r600_translate_colorswap(surf->base.format);
- unsigned block_size =
- align(util_format_get_blocksize(pipe_buffer->format), 4);
- unsigned pitch_alignment =
- MAX2(64, rctx->screen->b.tiling_info.group_bytes / block_size);
- unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
-
- /* XXX: This is copied from evergreen_init_color_surface(). I don't
- * know why this is necessary.
- */
- if (pipe_buffer->usage == PIPE_USAGE_STAGING) {
- endian = ENDIAN_NONE;
+ ntype = V_028C70_NUMBER_UNORM;
+ if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+ ntype = V_028C70_NUMBER_SRGB;
+ else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
+ if (desc->channel[i].normalized)
+ ntype = V_028C70_NUMBER_SNORM;
+ else if (desc->channel[i].pure_integer)
+ ntype = V_028C70_NUMBER_SINT;
+ } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
+ if (desc->channel[i].normalized)
+ ntype = V_028C70_NUMBER_UNORM;
+ else if (desc->channel[i].pure_integer)
+ ntype = V_028C70_NUMBER_UINT;
}
-
- surf->cb_color_base = r600_resource(pipe_buffer)->gpu_address >> 8;
-
- surf->cb_color_pitch = (pitch / 8) - 1;
-
- surf->cb_color_slice = 0;
-
- surf->cb_color_view = 0;
-
- surf->cb_color_info =
- S_028C70_ENDIAN(endian)
- | S_028C70_FORMAT(format)
- | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
- | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
- | S_028C70_COMP_SWAP(swap)
- | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
- * are using NUMBER_UINT */
- | S_028C70_RAT(1)
- ;
-
- surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
-
- /* For buffers, CB_COLOR0_DIM needs to be set to the number of
- * elements. */
- surf->cb_color_dim = pipe_buffer->width0;
-
- /* Set the buffer range the GPU will have access to: */
- util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
- 0, pipe_buffer->width0);
-
- surf->cb_color_fmask = surf->cb_color_base;
- surf->cb_color_fmask_slice = 0;
+ pitch = (pitch / 8) - 1;
+ color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
+
+ color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
+ color->info |= S_028C70_FORMAT(format) |
+ S_028C70_COMP_SWAP(swap) |
+ S_028C70_BLEND_CLAMP(0) |
+ S_028C70_BLEND_BYPASS(1) |
+ S_028C70_NUMBER_TYPE(ntype) |
+ S_028C70_ENDIAN(endian);
+ color->attrib = S_028C74_NON_DISP_TILING_ORDER(1);
+ color->ntype = ntype;
+ color->export_16bpc = false;
+ color->dim = width_elements - 1;
+ color->slice = 0; /* (width_elements / 64) - 1;*/
+ color->view = 0;
+ color->offset = res->gpu_address >> 8;
+
+ color->fmask = color->offset;
+ color->fmask_slice = 0;
}
-void evergreen_init_color_surface(struct r600_context *rctx,
- struct r600_surface *surf)
+static void evergreen_set_color_surface_common(struct r600_context *rctx,
+ struct r600_texture *rtex,
+ unsigned level,
+ unsigned first_layer,
+ unsigned last_layer,
+ enum pipe_format pformat,
+ struct r600_tex_color_info *color)
{
struct r600_screen *rscreen = rctx->screen;
- struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
- unsigned level = surf->base.u.tex.level;
unsigned pitch, slice;
- unsigned color_info, color_attrib, color_dim = 0, color_view;
- unsigned format, swap, ntype, endian;
- uint64_t offset, base_offset;
unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
+ unsigned format, swap, ntype, endian;
const struct util_format_description *desc;
+ bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
int i;
- bool blend_clamp = 0, blend_bypass = 0;
-
- offset = rtex->surface.level[level].offset;
- if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
- assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
- offset += rtex->surface.level[level].slice_size *
- surf->base.u.tex.first_layer;
- color_view = 0;
- } else
- color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
- S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
-
- pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
- slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
+
+ color->offset = rtex->surface.u.legacy.level[level].offset;
+ color->view = S_028C6C_SLICE_START(first_layer) |
+ S_028C6C_SLICE_MAX(last_layer);
+
+ color->offset += rtex->resource.gpu_address;
+ color->offset >>= 8;
+
+ color->dim = 0;
+ pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1;
+ slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
if (slice) {
slice = slice - 1;
}
- color_info = 0;
- switch (rtex->surface.level[level].mode) {
+
+ color->info = 0;
+ switch (rtex->surface.u.legacy.level[level].mode) {
+ default:
case RADEON_SURF_MODE_LINEAR_ALIGNED:
- color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
+ color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
non_disp_tiling = 1;
break;
case RADEON_SURF_MODE_1D:
- color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
+ color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
non_disp_tiling = rtex->non_disp_tiling;
break;
case RADEON_SURF_MODE_2D:
- color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
+ color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
non_disp_tiling = rtex->non_disp_tiling;
break;
- case RADEON_SURF_MODE_LINEAR:
- default:
- color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
- non_disp_tiling = 1;
- break;
}
- tile_split = rtex->surface.tile_split;
- macro_aspect = rtex->surface.mtilea;
- bankw = rtex->surface.bankw;
- bankh = rtex->surface.bankh;
+ tile_split = rtex->surface.u.legacy.tile_split;
+ macro_aspect = rtex->surface.u.legacy.mtilea;
+ bankw = rtex->surface.u.legacy.bankw;
+ bankh = rtex->surface.u.legacy.bankh;
if (rtex->fmask.size)
fmask_bankh = rtex->fmask.bank_height;
else
- fmask_bankh = rtex->surface.bankh;
+ fmask_bankh = rtex->surface.u.legacy.bankh;
tile_split = eg_tile_split(tile_split);
macro_aspect = eg_macro_tile_aspect(macro_aspect);
bankw = eg_bank_wh(bankw);
bankh = eg_bank_wh(bankh);
fmask_bankh = eg_bank_wh(fmask_bankh);
- /* 128 bit formats require tile type = 1 */
if (rscreen->b.chip_class == CAYMAN) {
- if (util_format_get_blocksize(surf->base.format) >= 16)
+ if (util_format_get_blocksize(pformat) >= 16)
non_disp_tiling = 1;
}
- nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
- desc = util_format_description(surf->base.format);
+ nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
+ desc = util_format_description(pformat);
for (i = 0; i < 4; i++) {
if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
break;
}
}
-
- color_attrib = S_028C74_TILE_SPLIT(tile_split)|
- S_028C74_NUM_BANKS(nbanks) |
- S_028C74_BANK_WIDTH(bankw) |
- S_028C74_BANK_HEIGHT(bankh) |
- S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
- S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
- S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
+ color->attrib = S_028C74_TILE_SPLIT(tile_split)|
+ S_028C74_NUM_BANKS(nbanks) |
+ S_028C74_BANK_WIDTH(bankw) |
+ S_028C74_BANK_HEIGHT(bankh) |
+ S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
+ S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
+ S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
if (rctx->b.chip_class == CAYMAN) {
- color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
- UTIL_FORMAT_SWIZZLE_1);
+ color->attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
+ PIPE_SWIZZLE_1);
if (rtex->resource.b.b.nr_samples > 1) {
unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
- color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
+ color->attrib |= S_028C74_NUM_SAMPLES(log_samples) |
S_028C74_NUM_FRAGMENTS(log_samples);
}
}
ntype = V_028C70_NUMBER_UINT;
}
- format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
- assert(format != ~0);
+ if (R600_BIG_ENDIAN)
+ do_endian_swap = !rtex->db_compatible;
- swap = r600_translate_colorswap(surf->base.format);
+ format = r600_translate_colorformat(rctx->b.chip_class, pformat, do_endian_swap);
+ assert(format != ~0);
+ swap = r600_translate_colorswap(pformat, do_endian_swap);
assert(swap != ~0);
- if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
- endian = ENDIAN_NONE;
- } else {
- endian = r600_colorformat_endian_swap(format);
- }
+ endian = r600_colorformat_endian_swap(format, do_endian_swap);
/* blend clamp should be set for all NORM/SRGB types */
if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
blend_bypass = 1;
}
- surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
-
- color_info |= S_028C70_FORMAT(format) |
+ color->ntype = ntype;
+ color->info |= S_028C70_FORMAT(format) |
S_028C70_COMP_SWAP(swap) |
S_028C70_BLEND_CLAMP(blend_clamp) |
S_028C70_BLEND_BYPASS(blend_bypass) |
S_028C70_NUMBER_TYPE(ntype) |
S_028C70_ENDIAN(endian);
+ if (rtex->fmask.size) {
+ color->info |= S_028C70_COMPRESSION(1);
+ }
+
/* EXPORT_NORM is an optimzation that can be enabled for better
* performance in certain cases.
* EXPORT_NORM can be enabled if:
* - 11-bit or smaller UNORM/SNORM/SRGB
* - 16-bit or smaller FLOAT
*/
+ color->export_16bpc = false;
if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
((desc->channel[i].size < 12 &&
desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
(desc->channel[i].size < 17 &&
desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
- color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
- surf->export_16bpc = true;
+ color->info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
+ color->export_16bpc = true;
}
+ color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
+ color->slice = S_028C68_SLICE_TILE_MAX(slice);
+
if (rtex->fmask.size) {
- color_info |= S_028C70_COMPRESSION(1);
+ color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8;
+ color->fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
+ } else {
+ color->fmask = color->offset;
+ color->fmask_slice = S_028C88_TILE_MAX(slice);
}
+}
- base_offset = rtex->resource.gpu_address;
+/**
+ * This function intializes the CB* register values for RATs. It is meant
+ * to be used for 1D aligned buffers that do not have an associated
+ * radeon_surf.
+ */
+void evergreen_init_color_surface_rat(struct r600_context *rctx,
+ struct r600_surface *surf)
+{
+ struct pipe_resource *pipe_buffer = surf->base.texture;
+ struct r600_tex_color_info color;
+
+ evergreen_set_color_surface_buffer(rctx, (struct r600_resource *)surf->base.texture,
+ surf->base.format, 0, pipe_buffer->width0,
+ &color);
+
+ surf->cb_color_base = color.offset;
+ surf->cb_color_dim = color.dim;
+ surf->cb_color_info = color.info | S_028C70_RAT(1);
+ surf->cb_color_pitch = color.pitch;
+ surf->cb_color_slice = color.slice;
+ surf->cb_color_view = color.view;
+ surf->cb_color_attrib = color.attrib;
+ surf->cb_color_fmask = color.fmask;
+ surf->cb_color_fmask_slice = color.fmask_slice;
+
+ surf->cb_color_view = 0;
+
+ /* Set the buffer range the GPU will have access to: */
+ util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
+ 0, pipe_buffer->width0);
+}
+
+
+void evergreen_init_color_surface(struct r600_context *rctx,
+ struct r600_surface *surf)
+{
+ struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
+ unsigned level = surf->base.u.tex.level;
+ struct r600_tex_color_info color;
+
+ evergreen_set_color_surface_common(rctx, rtex, level,
+ surf->base.u.tex.first_layer,
+ surf->base.u.tex.last_layer,
+ surf->base.format,
+ &color);
+
+ surf->alphatest_bypass = color.ntype == V_028C70_NUMBER_UINT ||
+ color.ntype == V_028C70_NUMBER_SINT;
+ surf->export_16bpc = color.export_16bpc;
/* XXX handle enabling of CB beyond BASE8 which has different offset */
- surf->cb_color_base = (base_offset + offset) >> 8;
- surf->cb_color_dim = color_dim;
- surf->cb_color_info = color_info;
- surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
- surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
- surf->cb_color_view = color_view;
- surf->cb_color_attrib = color_attrib;
- if (rtex->fmask.size) {
- surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
- surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
- } else {
- surf->cb_color_fmask = surf->cb_color_base;
- surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
- }
+ surf->cb_color_base = color.offset;
+ surf->cb_color_dim = color.dim;
+ surf->cb_color_info = color.info;
+ surf->cb_color_pitch = color.pitch;
+ surf->cb_color_slice = color.slice;
+ surf->cb_color_view = color.view;
+ surf->cb_color_attrib = color.attrib;
+ surf->cb_color_fmask = color.fmask;
+ surf->cb_color_fmask_slice = color.fmask_slice;
surf->color_initialized = true;
}
struct r600_screen *rscreen = rctx->screen;
struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
unsigned level = surf->base.u.tex.level;
- struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
+ struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
uint64_t offset;
unsigned format, array_mode;
unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
assert(format != ~0);
offset = rtex->resource.gpu_address;
- offset += rtex->surface.level[level].offset;
+ offset += rtex->surface.u.legacy.level[level].offset;
- switch (rtex->surface.level[level].mode) {
+ switch (rtex->surface.u.legacy.level[level].mode) {
case RADEON_SURF_MODE_2D:
array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
break;
case RADEON_SURF_MODE_1D:
case RADEON_SURF_MODE_LINEAR_ALIGNED:
- case RADEON_SURF_MODE_LINEAR:
default:
array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
break;
}
- tile_split = rtex->surface.tile_split;
- macro_aspect = rtex->surface.mtilea;
- bankw = rtex->surface.bankw;
- bankh = rtex->surface.bankh;
+ tile_split = rtex->surface.u.legacy.tile_split;
+ macro_aspect = rtex->surface.u.legacy.mtilea;
+ bankw = rtex->surface.u.legacy.bankw;
+ bankh = rtex->surface.u.legacy.bankh;
tile_split = eg_tile_split(tile_split);
macro_aspect = eg_macro_tile_aspect(macro_aspect);
bankw = eg_bank_wh(bankw);
bankh = eg_bank_wh(bankh);
- nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
+ nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
offset >>= 8;
surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
levelinfo->nblk_y / 64 - 1);
- switch (surf->base.format) {
- case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- case PIPE_FORMAT_X8Z24_UNORM:
- case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- surf->pa_su_poly_offset_db_fmt_cntl =
- S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
- break;
- case PIPE_FORMAT_Z32_FLOAT:
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- surf->pa_su_poly_offset_db_fmt_cntl =
- S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
- S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
- break;
- case PIPE_FORMAT_Z16_UNORM:
- surf->pa_su_poly_offset_db_fmt_cntl =
- S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
- break;
- default:;
- }
-
if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
uint64_t stencil_offset;
- unsigned stile_split = rtex->surface.stencil_tile_split;
+ unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
stile_split = eg_tile_split(stile_split);
- stencil_offset = rtex->surface.stencil_level[level].offset;
+ stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset;
stencil_offset += rtex->resource.gpu_address;
surf->db_stencil_base = stencil_offset >> 8;
}
/* use htile only for first level */
- if (rtex->htile_buffer && !level) {
- uint64_t va = rtex->htile_buffer->gpu_address;
+ if (rtex->htile_offset && !level) {
+ uint64_t va = rtex->resource.gpu_address + rtex->htile_offset;
surf->db_htile_data_base = va >> 8;
surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
S_028ABC_HTILE_HEIGHT(1) |
struct r600_texture *rtex;
uint32_t i, log_samples;
- if (rctx->framebuffer.state.nr_cbufs) {
- rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
- rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
- R600_CONTEXT_FLUSH_AND_INV_CB_META;
- }
- if (rctx->framebuffer.state.zsbuf) {
- rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
- rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
-
- rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
- if (rtex->htile_buffer) {
- rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
- }
- }
+ /* Flush TC when changing the framebuffer state, because the only
+ * client not using TC that can change textures is the framebuffer.
+ * Other places don't typically have to flush TC.
+ */
+ rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
+ R600_CONTEXT_FLUSH_AND_INV |
+ R600_CONTEXT_FLUSH_AND_INV_CB |
+ R600_CONTEXT_FLUSH_AND_INV_CB_META |
+ R600_CONTEXT_FLUSH_AND_INV_DB |
+ R600_CONTEXT_FLUSH_AND_INV_DB_META |
+ R600_CONTEXT_INV_TEX_CACHE;
util_copy_framebuffer_state(&rctx->framebuffer.state, state);
rctx->framebuffer.export_16bpc = false;
}
- if (rtex->fmask.size && rtex->cmask.size) {
+ if (rtex->fmask.size) {
rctx->framebuffer.compressed_cb_mask |= 1 << i;
}
}
/* Colorbuffers. */
rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
- if (rctx->keep_tiling_flags)
- rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
+ rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
/* ZS buffer. */
if (state->zsbuf) {
rctx->framebuffer.atom.num_dw += 24;
- if (rctx->keep_tiling_flags)
- rctx->framebuffer.atom.num_dw += 2;
+ rctx->framebuffer.atom.num_dw += 2;
} else if (rctx->screen->b.info.drm_minor >= 18) {
rctx->framebuffer.atom.num_dw += 4;
}
r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
r600_set_sample_locations_constant_buffer(rctx);
+ rctx->framebuffer.do_update_surf_dirtiness = true;
}
static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
nr_samples = 0;
break;
case 2:
- radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_2x));
- radeon_emit_array(cs, eg_sample_locs_2x, Elements(eg_sample_locs_2x));
+ radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
+ radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
max_dist = eg_max_dist_2x;
break;
case 4:
- radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_4x));
- radeon_emit_array(cs, eg_sample_locs_4x, Elements(eg_sample_locs_4x));
+ radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
+ radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
max_dist = eg_max_dist_4x;
break;
case 8:
- radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
- radeon_emit_array(cs, sample_locs_8x, Elements(sample_locs_8x));
+ radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
+ radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
max_dist = max_dist_8x;
break;
}
S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
- radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1));
+ radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
+ EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
+ EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
+ EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
} else {
radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
- radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, 0);
+ radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
+ EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
+ EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
}
}
&rctx->b.gfx,
(struct r600_resource*)cb->base.texture,
RADEON_USAGE_READWRITE,
- tex->surface.nsamples > 1 ?
+ tex->resource.b.b.nr_samples > 1 ?
RADEON_PRIO_COLOR_BUFFER_MSAA :
RADEON_PRIO_COLOR_BUFFER);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
radeon_emit(cs, reloc);
- if (!rctx->keep_tiling_flags) {
- radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
- radeon_emit(cs, reloc);
- }
-
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
radeon_emit(cs, reloc);
radeon_emit(cs, reloc);
}
/* set CB_COLOR1_INFO for possible dual-src blending */
- if (i == 1 && state->cbufs[0]) {
+ if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) {
radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
cb->cb_color_info | tex->cb_color_info);
-
- if (!rctx->keep_tiling_flags) {
- unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
- &rctx->b.gfx,
- (struct r600_resource*)state->cbufs[0]->texture,
- RADEON_USAGE_READWRITE,
- RADEON_PRIO_COLOR_BUFFER);
-
- radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
- radeon_emit(cs, reloc);
- }
i++;
}
- if (rctx->keep_tiling_flags) {
- for (; i < 8 ; i++) {
- radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
- }
- for (; i < 12; i++) {
- radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
- }
- }
+ for (; i < 8 ; i++)
+ radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
+ for (; i < 12; i++)
+ radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
/* ZS buffer. */
if (state->zsbuf) {
RADEON_PRIO_DEPTH_BUFFER_MSAA :
RADEON_PRIO_DEPTH_BUFFER);
- radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
- zb->pa_su_poly_offset_db_fmt_cntl);
radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
- if (!rctx->keep_tiling_flags) {
- radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
- radeon_emit(cs, reloc);
- }
-
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
radeon_emit(cs, reloc);
if (rctx->b.chip_class == EVERGREEN) {
evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
} else {
- cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
- cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples, rctx->ps_iter_samples, 0);
+ unsigned sc_mode_cntl_1 =
+ EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
+ EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
+
+ if (rctx->framebuffer.nr_samples > 1)
+ cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
+ cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples,
+ rctx->ps_iter_samples, 0, sc_mode_cntl_1);
}
}
struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
float offset_units = state->offset_units;
float offset_scale = state->offset_scale;
+ uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
- switch (state->zs_format) {
- case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- case PIPE_FORMAT_X8Z24_UNORM:
- case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- offset_units *= 2.0f;
- break;
- case PIPE_FORMAT_Z16_UNORM:
- offset_units *= 4.0f;
- break;
- default:;
+ if (!state->offset_units_unscaled) {
+ switch (state->zs_format) {
+ case PIPE_FORMAT_Z24X8_UNORM:
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ case PIPE_FORMAT_X8Z24_UNORM:
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+ offset_units *= 2.0f;
+ pa_su_poly_offset_db_fmt_cntl =
+ S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
+ break;
+ case PIPE_FORMAT_Z16_UNORM:
+ offset_units *= 4.0f;
+ pa_su_poly_offset_db_fmt_cntl =
+ S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
+ break;
+ default:
+ pa_su_poly_offset_db_fmt_cntl =
+ S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
+ S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+ }
}
radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
radeon_emit(cs, fui(offset_units));
radeon_emit(cs, fui(offset_scale));
radeon_emit(cs, fui(offset_units));
+
+ radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
+ pa_su_poly_offset_db_fmt_cntl);
}
static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
- reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
+ reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
- cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
- cs->buf[cs->cdw++] = reloc_idx;
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+ radeon_emit(cs, reloc_idx);
} else {
radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
unsigned db_count_control = 0;
unsigned db_render_override =
S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
- S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
- /* There is a hang with HTILE if stencil is used and
- * fast stencil is enabled. */
- S_02800C_FAST_STENCIL_DISABLE(1);
+ S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
- if (a->occlusion_query_enabled) {
+ if (rctx->b.num_occlusion_queries > 0 &&
+ !a->occlusion_queries_disabled) {
db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
if (rctx->b.chip_class == CAYMAN) {
db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
}
db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
- }
- /* FIXME we should be able to use hyperz even if we are not writing to
- * zbuffer but somehow this trigger GPU lockup. See :
- *
- * https://bugs.freedesktop.org/show_bug.cgi?id=60848
- *
- * Disable hyperz for now if not writing to zbuffer.
- */
- if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface && rctx->zwritemask) {
- /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
- db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
- /* This is to fix a lockup when hyperz and alpha test are enabled at
- * the same time somehow GPU get confuse on which order to pick for
- * z test
- */
- if (rctx->alphatest_state.sx_alpha_test_control) {
- db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
- }
} else {
- db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
+ db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
}
+
+ /* This is to fix a lockup when hyperz and alpha test are enabled at
+ * the same time somehow GPU get confuse on which order to pick for
+ * z test
+ */
+ if (rctx->alphatest_state.sx_alpha_test_control)
+ db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
+
if (a->flush_depthstencil_through_cb) {
assert(a->copy_depth || a->copy_stencil);
unsigned buffer_index = u_bit_scan(&dirty_mask);
vb = &state->vb[buffer_index];
- rbuffer = (struct r600_resource*)vb->buffer;
+ rbuffer = (struct r600_resource*)vb->buffer.resource;
assert(rbuffer);
va = rbuffer->gpu_address + vb->buffer_offset;
if (!gs_ring_buffer) {
radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
- ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags);
+ DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
pkt_flags);
}
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
RADEON_USAGE_READ,
- RADEON_PRIO_INTERNAL_SHADER));
+ RADEON_PRIO_SHADER_BINARY));
}
static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
- RADEON_PRIO_RINGS_STREAMOUT));
+ RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
state->esgs_ring.buffer_size >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
- RADEON_PRIO_RINGS_STREAMOUT));
+ RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
state->gsvs_ring.buffer_size >> 8);
} else {
static void cayman_init_atom_start_cs(struct r600_context *rctx)
{
struct r600_command_buffer *cb = &rctx->start_cs_cmd;
- int tmp, i;
+ int i;
- r600_init_command_buffer(cb, 336);
+ r600_init_command_buffer(cb, 338);
/* This must be first. */
r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
+ /* This enables pipeline stat & streamout queries.
+ * They are only disabled by blits.
+ */
+ r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
+
cayman_init_common_regs(cb, rctx->b.chip_class,
rctx->b.family, rctx->screen->b.info.drm_minor);
r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
+ /* remove LS/HS from one SIMD for hw workaround */
+ r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
+ r600_store_value(cb, 0xffffffff);
+ r600_store_value(cb, 0xffffffff);
+ r600_store_value(cb, 0xfffffffe);
+
r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
- r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
- r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
- r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
-
r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
- r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
- for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
- r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
- r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
- }
-
r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
- r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
- r600_store_value(cb, fui(1.0)); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
- r600_store_value(cb, fui(1.0)); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
- r600_store_value(cb, fui(1.0)); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
- r600_store_value(cb, fui(1.0)); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
-
r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
return;
}
- r600_init_command_buffer(cb, 342);
+ r600_init_command_buffer(cb, 338);
/* This must be first. */
r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
+ /* This enables pipeline stat & streamout queries.
+ * They are only disabled by blits.
+ */
+ r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
+
evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
rctx->b.family, rctx->screen->b.info.drm_minor);
r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
+ /* remove LS/HS from one SIMD for hw workaround */
r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
r600_store_value(cb, 0xffffffff);
r600_store_value(cb, 0xffffffff);
r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
- r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
- r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
- r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
-
r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
- r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
- for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
- r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
- r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
- }
-
r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
- r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
- r600_store_value(cb, fui(1.0)); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
- r600_store_value(cb, fui(1.0)); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
- r600_store_value(cb, fui(1.0)); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
- r600_store_value(cb, fui(1.0)); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
-
r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
if (sid) {
tmp = S_028644_SEMANTIC(sid);
+ /* D3D 9 behaviour. GL is undefined */
+ if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
+ tmp |= S_028644_DEFAULT_VAL(3);
+
if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
uint64_t base, addr;
- dst_mode = rdst->surface.level[dst_level].mode;
- src_mode = rsrc->surface.level[src_level].mode;
- /* downcast linear aligned to linear to simplify test */
- src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
- dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
+ dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
+ src_mode = rsrc->surface.u.legacy.level[src_level].mode;
assert(dst_mode != src_mode);
/* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
sub_cmd = EG_DMA_COPY_TILED;
lbpp = util_logbase2(bpp);
pitch_tile_max = ((pitch / bpp) / 8) - 1;
- nbanks = eg_num_banks(rctx->screen->b.tiling_info.num_banks);
+ nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
- if (dst_mode == RADEON_SURF_MODE_LINEAR) {
+ if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
/* T2L */
array_mode = evergreen_array_mode(src_mode);
- slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
+ slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height, it's ok even
* if the linear destination/source have smaller heigh as the size of the
* dma packet will be using the copy_height which is always smaller or equal
* to the linear height
*/
- height = rsrc->surface.level[src_level].npix_y;
+ height = u_minify(rsrc->resource.b.b.height0, src_level);
detile = 1;
x = src_x;
y = src_y;
z = src_z;
- base = rsrc->surface.level[src_level].offset;
- addr = rdst->surface.level[dst_level].offset;
- addr += rdst->surface.level[dst_level].slice_size * dst_z;
+ base = rsrc->surface.u.legacy.level[src_level].offset;
+ addr = rdst->surface.u.legacy.level[dst_level].offset;
+ addr += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
addr += dst_y * pitch + dst_x * bpp;
- bank_h = eg_bank_wh(rsrc->surface.bankh);
- bank_w = eg_bank_wh(rsrc->surface.bankw);
- mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
- tile_split = eg_tile_split(rsrc->surface.tile_split);
+ bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
+ bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw);
+ mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea);
+ tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split);
base += rsrc->resource.gpu_address;
addr += rdst->resource.gpu_address;
} else {
/* L2T */
array_mode = evergreen_array_mode(dst_mode);
- slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
+ slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height, it's ok even
* if the linear destination/source have smaller heigh as the size of the
* dma packet will be using the copy_height which is always smaller or equal
* to the linear height
*/
- height = rdst->surface.level[dst_level].npix_y;
+ height = u_minify(rdst->resource.b.b.height0, dst_level);
detile = 0;
x = dst_x;
y = dst_y;
z = dst_z;
- base = rdst->surface.level[dst_level].offset;
- addr = rsrc->surface.level[src_level].offset;
- addr += rsrc->surface.level[src_level].slice_size * src_z;
+ base = rdst->surface.u.legacy.level[dst_level].offset;
+ addr = rsrc->surface.u.legacy.level[src_level].offset;
+ addr += rsrc->surface.u.legacy.level[src_level].slice_size * src_z;
addr += src_y * pitch + src_x * bpp;
- bank_h = eg_bank_wh(rdst->surface.bankh);
- bank_w = eg_bank_wh(rdst->surface.bankw);
- mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
- tile_split = eg_tile_split(rdst->surface.tile_split);
+ bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh);
+ bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw);
+ mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea);
+ tile_split = eg_tile_split(rdst->surface.u.legacy.tile_split);
base += rdst->resource.gpu_address;
addr += rsrc->resource.gpu_address;
}
size = (copy_height * pitch) / 4;
ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
- r600_need_dma_space(&rctx->b, ncopy * 9);
+ r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
for (i = 0; i < ncopy; i++) {
cheight = copy_height;
RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
- cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
- cs->buf[cs->cdw++] = base >> 8;
- cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
- (lbpp << 24) | (bank_h << 21) |
- (bank_w << 18) | (mt_aspect << 16);
- cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
- cs->buf[cs->cdw++] = (slice_tile_max << 0);
- cs->buf[cs->cdw++] = (x << 0) | (z << 18);
- cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28);
- cs->buf[cs->cdw++] = addr & 0xfffffffc;
- cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
+ radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
+ radeon_emit(cs, base >> 8);
+ radeon_emit(cs, (detile << 31) | (array_mode << 27) |
+ (lbpp << 24) | (bank_h << 21) |
+ (bank_w << 18) | (mt_aspect << 16));
+ radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
+ radeon_emit(cs, (slice_tile_max << 0));
+ radeon_emit(cs, (x << 0) | (z << 18));
+ radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
+ radeon_emit(cs, addr & 0xfffffffc);
+ radeon_emit(cs, (addr >> 32UL) & 0xff);
copy_height -= cheight;
addr += cheight * pitch;
y += cheight;
return;
}
- if (src->format != dst->format || src_box->depth > 1 ||
- (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level)) {
+ if (src_box->depth > 1 ||
+ !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
+ dstz, rsrc, src_level, src_box))
goto fallback;
- }
-
- if (rsrc->dirty_level_mask & (1 << src_level)) {
- ctx->flush_resource(ctx, src);
- }
src_x = util_format_get_nblocksx(src->format, src_box->x);
dst_x = util_format_get_nblocksx(src->format, dst_x);
dst_y = util_format_get_nblocksy(src->format, dst_y);
bpp = rdst->surface.bpe;
- dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
- src_pitch = rsrc->surface.level[src_level].pitch_bytes;
- src_w = rsrc->surface.level[src_level].npix_x;
- dst_w = rdst->surface.level[dst_level].npix_x;
+ dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
+ src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
+ src_w = u_minify(rsrc->resource.b.b.width0, src_level);
+ dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
copy_height = src_box->height / rsrc->surface.blk_h;
- dst_mode = rdst->surface.level[dst_level].mode;
- src_mode = rsrc->surface.level[src_level].mode;
- /* downcast linear aligned to linear to simplify test */
- src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
- dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
+ dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
+ src_mode = rsrc->surface.u.legacy.level[src_level].mode;
if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
/* FIXME evergreen can do partial blit */
* dst_x/y == 0
* dst_pitch == src_pitch
*/
- src_offset= rsrc->surface.level[src_level].offset;
- src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
+ src_offset= rsrc->surface.u.legacy.level[src_level].offset;
+ src_offset += rsrc->surface.u.legacy.level[src_level].slice_size * src_box->z;
src_offset += src_y * src_pitch + src_x * bpp;
- dst_offset = rdst->surface.level[dst_level].offset;
- dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
+ dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
+ dst_offset += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
dst_offset += dst_y * dst_pitch + dst_x * bpp;
evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
src_box->height * src_pitch);
unsigned id = 1;
unsigned i;
/* !!!
- * To avoid GPU lockup registers must be emited in a specific order
+ * To avoid GPU lockup registers must be emitted in a specific order
* (no kidding ...). The order below is important and have been
- * partialy infered from analyzing fglrx command stream.
+ * partially inferred from analyzing fglrx command stream.
*
* Don't reorder atom without carefully checking the effect (GPU lockup
* or piglit regression).
*/
if (rctx->b.chip_class == EVERGREEN) {
r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
- if (rctx->screen->b.info.drm_minor >= 7)
- rctx->config_state.dyn_gpr_enabled = true;
+ rctx->config_state.dyn_gpr_enabled = true;
}
r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
/* shader const */
r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
- r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
+ r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
- r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
+ r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
- r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 0);
- r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 0);
+ r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
+ r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
rctx->b.b.set_min_samples = evergreen_set_min_samples;
- rctx->b.b.set_scissor_states = evergreen_set_scissor_states;
rctx->b.b.set_tess_state = evergreen_set_tess_state;
if (rctx->b.chip_class == EVERGREEN)
rctx->b.b.get_sample_position = evergreen_get_sample_position;
unsigned output_patch0_offset, perpatch_output_offset, lds_size;
uint32_t values[16];
unsigned num_waves;
- unsigned num_pipes = rctx->screen->b.info.r600_max_pipes;
+ unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
unsigned wave_divisor = (16 * num_pipes);
*num_patches = 1;
max_gprs += def_num_clause_temp_gprs * 2;
/* if we have no TESS and dyn gpr is enabled then do nothing. */
- if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader || rctx->screen->b.info.drm_minor < 7) {
+ if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
if (rctx->config_state.dyn_gpr_enabled)
return true;
}
return true;
}
+
+#define AC_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
+
+void eg_trace_emit(struct r600_context *rctx)
+{
+ struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
+ unsigned reloc;
+
+ if (rctx->b.chip_class < EVERGREEN)
+ return;
+
+ /* This must be done after r600_need_cs_space. */
+ reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
+ (struct r600_resource*)rctx->trace_buf, RADEON_USAGE_WRITE,
+ RADEON_PRIO_CP_DMA);
+
+ rctx->trace_id++;
+ radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rctx->trace_buf,
+ RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
+ radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
+ radeon_emit(cs, rctx->trace_buf->gpu_address);
+ radeon_emit(cs, rctx->trace_buf->gpu_address >> 32 | MEM_WRITE_32_BITS | MEM_WRITE_CONFIRM);
+ radeon_emit(cs, rctx->trace_id);
+ radeon_emit(cs, 0);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+ radeon_emit(cs, reloc);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+ radeon_emit(cs, AC_ENCODE_TRACE_POINT(rctx->trace_id));
+}
projects / mesa.git / blobdiff