blend->cb_target_mask = target_mask;
r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
- color_control, 0xFFFFFFFD, NULL, 0);
+ color_control, 0xFFFFFFFF, NULL, 0);
if (rctx->chip_class != CAYMAN)
r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
- unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
- unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
+ unsigned db_depth_control, alpha_test_control, alpha_ref;
+ unsigned db_render_override, db_render_control;
struct r600_pipe_state *rstate;
if (dsa == NULL) {
return NULL;
}
+ dsa->valuemask[0] = state->stencil[0].valuemask;
+ dsa->valuemask[1] = state->stencil[1].valuemask;
+ dsa->writemask[0] = state->stencil[0].writemask;
+ dsa->writemask[1] = state->stencil[1].writemask;
+
rstate = &dsa->rstate;
rstate->id = R600_PIPE_STATE_DSA;
- /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
- db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
- stencil_ref_mask = 0;
- stencil_ref_mask_bf = 0;
db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
S_028800_ZFUNC(state->depth.func);
db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
-
- stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
- S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
if (state->stencil[1].enabled) {
db_depth_control |= S_028800_BACKFACE_ENABLE(1);
db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
- stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
- S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
}
}
r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(rstate,
- R_028430_DB_STENCILREFMASK, stencil_ref_mask,
- 0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
- r600_pipe_state_add_reg(rstate,
- R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
- 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
/* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
* STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
* evergreen_pipe_shader_ps().*/
- r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL, 0);
unsigned tmp;
unsigned prov_vtx = 1, polygon_dual_mode;
unsigned clip_rule;
+ float psize_min, psize_max;
if (rs == NULL) {
return NULL;
S_028814_POLY_MODE(polygon_dual_mode) |
S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
- S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex),
- S_02881C_USE_VTX_POINT_SIZE(1), NULL, 0);
r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
/* point size 12.4 fixed point */
tmp = (unsigned)(state->point_size * 8.0);
r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL, 0);
+
+ if (state->point_size_per_vertex) {
+ psize_min = util_get_min_point_size(state);
+ psize_max = 8192;
+ } else {
+ /* Force the point size to be as if the vertex output was disabled. */
+ psize_min = state->point_size;
+ psize_max = state->point_size;
+ }
+ /* Divide by two, because 0.5 = 1 pixel. */
+ r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
+ S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
+ S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
+ 0xFFFFFFFF, NULL, 0);
tmp = (unsigned)state->line_width * 8;
r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
r600_context_pipe_state_set(&rctx->ctx, rstate);
}
-static void evergreen_set_stencil_ref(struct pipe_context *ctx,
- const struct pipe_stencil_ref *state)
-{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
- struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- u32 tmp;
-
- if (rstate == NULL)
- return;
-
- rctx->stencil_ref = *state;
- rstate->id = R600_PIPE_STATE_STENCIL_REF;
- tmp = S_028430_STENCILREF(state->ref_value[0]);
- r600_pipe_state_add_reg(rstate,
- R_028430_DB_STENCILREFMASK, tmp,
- ~C_028430_STENCILREF, NULL, 0);
- tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
- r600_pipe_state_add_reg(rstate,
- R_028434_DB_STENCILREFMASK_BF, tmp,
- ~C_028434_STENCILREF_BF, NULL, 0);
-
- free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
- rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
- r600_context_pipe_state_set(&rctx->ctx, rstate);
-}
-
static void evergreen_set_viewport_state(struct pipe_context *ctx,
const struct pipe_viewport_state *state)
{
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- u32 shader_mask, tl, br, target_mask;
+ u32 shader_mask, tl, br;
int tl_x, tl_y, br_x, br_y;
if (rstate == NULL)
rctx->ctx.num_dest_buffers++;
}
- target_mask = 0x00000000;
- target_mask = 0xFFFFFFFF;
shader_mask = 0;
for (int i = 0; i < state->nr_cbufs; i++) {
- target_mask ^= 0xf << (i * 4);
shader_mask |= 0xf << (i * 4);
}
tl_x = 0;
r600_pipe_state_add_reg(rstate,
R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
0xFFFFFFFF, NULL, 0);
-
- r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
- 0x00000000, target_mask, NULL, 0);
r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
shader_mask, 0xFFFFFFFF, NULL, 0);
rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
rctx->context.set_sample_mask = evergreen_set_sample_mask;
rctx->context.set_scissor_state = evergreen_set_scissor_state;
- rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
+ rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
rctx->context.set_index_buffer = r600_set_index_buffer;
rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
rstate->nregs = 0;
- db_shader_control = 0;
+ db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
for (i = 0; i < rshader->ninput; i++) {
/* evergreen NUM_INTERP only contains values interpolated into the LDS,
POSITION goes via GPRs from the SC so isn't counted */
r600_pipe_state_add_reg(rstate,
R_02884C_SQ_PGM_EXPORTS_PS,
exports_ps, 0xFFFFFFFF, NULL, 0);
- /* only set some bits here, the other bits are set in the dsa state */
- r600_pipe_state_add_reg(rstate,
- R_02880C_DB_SHADER_CONTROL,
+ r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
db_shader_control,
- S_02880C_Z_EXPORT_ENABLE(1) |
- S_02880C_STENCIL_EXPORT_ENABLE(1) |
- S_02880C_KILL_ENABLE(1),
- NULL, 0);
+ 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate,
R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
0xFFFFFFFF, NULL, 0);
R_02881C_PA_CL_VS_OUT_CNTL,
S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
- S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write),
+ S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
+ S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size),
S_02881C_VS_OUT_CCDIST0_VEC_ENA(1) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA(1) |
- S_02881C_VS_OUT_MISC_VEC_ENA(1),
+ S_02881C_VS_OUT_MISC_VEC_ENA(1) |
+ S_02881C_USE_VTX_POINT_SIZE(1),
NULL, 0);
}
memset(&dsa, 0, sizeof(dsa));
rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
- r600_pipe_state_add_reg(rstate,
- R_02880C_DB_SHADER_CONTROL,
- 0x0,
- S_02880C_DUAL_EXPORT_ENABLE(1), NULL, 0);
r600_pipe_state_add_reg(rstate,
R_028000_DB_RENDER_CONTROL,
S_028000_DEPTH_COPY_ENABLE(1) |
S_028000_STENCIL_COPY_ENABLE(1) |
S_028000_COPY_CENTROID(1),
- S_028000_DEPTH_COPY_ENABLE(1) |
- S_028000_STENCIL_COPY_ENABLE(1) |
- S_028000_COPY_CENTROID(1), NULL, 0);
+ 0xFFFFFFFF, NULL, 0);
return rstate;
}
projects / mesa.git / blobdiff