case PIPE_FORMAT_Z16_UNORM:
return V_028040_Z_16;
case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
return V_028040_Z_24;
case PIPE_FORMAT_Z32_FLOAT:
- case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
return V_028040_Z_32_FLOAT;
default:
return ~0U;
return V_028C70_SWAP_ALT;
case PIPE_FORMAT_A8_UNORM:
+ case PIPE_FORMAT_A8_UINT:
+ case PIPE_FORMAT_A8_SINT:
case PIPE_FORMAT_R4A4_UNORM:
return V_028C70_SWAP_ALT_REV;
case PIPE_FORMAT_I8_UNORM:
case PIPE_FORMAT_L8_UNORM:
+ case PIPE_FORMAT_I8_UINT:
+ case PIPE_FORMAT_I8_SINT:
+ case PIPE_FORMAT_L8_UINT:
+ case PIPE_FORMAT_L8_SINT:
case PIPE_FORMAT_L8_SRGB:
case PIPE_FORMAT_R8_UNORM:
case PIPE_FORMAT_R8_SNORM:
+ case PIPE_FORMAT_R8_UINT:
+ case PIPE_FORMAT_R8_SINT:
return V_028C70_SWAP_STD;
/* 16-bit buffers. */
return V_028C70_SWAP_STD;
case PIPE_FORMAT_L8A8_UNORM:
+ case PIPE_FORMAT_L8A8_UINT:
+ case PIPE_FORMAT_L8A8_SINT:
case PIPE_FORMAT_L8A8_SRGB:
return V_028C70_SWAP_ALT;
case PIPE_FORMAT_R8G8_UNORM:
+ case PIPE_FORMAT_R8G8_UINT:
+ case PIPE_FORMAT_R8G8_SINT:
return V_028C70_SWAP_STD;
case PIPE_FORMAT_R16_UNORM:
+ case PIPE_FORMAT_R16_UINT:
+ case PIPE_FORMAT_R16_SINT:
case PIPE_FORMAT_R16_FLOAT:
return V_028C70_SWAP_STD;
return V_028C70_SWAP_ALT_REV;
case PIPE_FORMAT_R8G8B8A8_SNORM:
case PIPE_FORMAT_R8G8B8A8_UNORM:
+ case PIPE_FORMAT_R8G8B8A8_SSCALED:
+ case PIPE_FORMAT_R8G8B8A8_USCALED:
+ case PIPE_FORMAT_R8G8B8A8_SINT:
+ case PIPE_FORMAT_R8G8B8A8_UINT:
case PIPE_FORMAT_R8G8B8X8_UNORM:
return V_028C70_SWAP_STD;
return V_028C70_SWAP_STD_REV;
case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
return V_028C70_SWAP_STD;
case PIPE_FORMAT_X8Z24_UNORM:
- case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
return V_028C70_SWAP_STD;
case PIPE_FORMAT_R10G10B10A2_UNORM:
return V_028C70_SWAP_STD;
case PIPE_FORMAT_B10G10R10A2_UNORM:
+ case PIPE_FORMAT_B10G10R10A2_UINT:
return V_028C70_SWAP_ALT;
case PIPE_FORMAT_R11G11B10_FLOAT:
case PIPE_FORMAT_R32_FLOAT:
+ case PIPE_FORMAT_R32_UINT:
+ case PIPE_FORMAT_R32_SINT:
case PIPE_FORMAT_Z32_FLOAT:
case PIPE_FORMAT_R16G16_FLOAT:
case PIPE_FORMAT_R16G16_UNORM:
+ case PIPE_FORMAT_R16G16_UINT:
+ case PIPE_FORMAT_R16G16_SINT:
return V_028C70_SWAP_STD;
/* 64-bit buffers. */
case PIPE_FORMAT_R32G32_FLOAT:
+ case PIPE_FORMAT_R32G32_UINT:
+ case PIPE_FORMAT_R32G32_SINT:
case PIPE_FORMAT_R16G16B16A16_UNORM:
case PIPE_FORMAT_R16G16B16A16_SNORM:
+ case PIPE_FORMAT_R16G16B16A16_USCALED:
+ case PIPE_FORMAT_R16G16B16A16_SSCALED:
+ case PIPE_FORMAT_R16G16B16A16_UINT:
+ case PIPE_FORMAT_R16G16B16A16_SINT:
case PIPE_FORMAT_R16G16B16A16_FLOAT:
- case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
/* 128-bit buffers. */
case PIPE_FORMAT_R32G32B32A32_FLOAT:
case PIPE_FORMAT_R32G32B32A32_SNORM:
case PIPE_FORMAT_R32G32B32A32_UNORM:
+ case PIPE_FORMAT_R32G32B32A32_SSCALED:
+ case PIPE_FORMAT_R32G32B32A32_USCALED:
+ case PIPE_FORMAT_R32G32B32A32_SINT:
+ case PIPE_FORMAT_R32G32B32A32_UINT:
return V_028C70_SWAP_STD;
default:
R600_ERR("unsupported colorswap format %d\n", format);
{
switch (format) {
/* 8-bit buffers. */
- case PIPE_FORMAT_L4A4_UNORM:
- case PIPE_FORMAT_R4A4_UNORM:
- case PIPE_FORMAT_A4R4_UNORM:
- return V_028C70_COLOR_4_4;
-
case PIPE_FORMAT_A8_UNORM:
+ case PIPE_FORMAT_A8_UINT:
+ case PIPE_FORMAT_A8_SINT:
case PIPE_FORMAT_I8_UNORM:
+ case PIPE_FORMAT_I8_UINT:
+ case PIPE_FORMAT_I8_SINT:
case PIPE_FORMAT_L8_UNORM:
+ case PIPE_FORMAT_L8_UINT:
+ case PIPE_FORMAT_L8_SINT:
case PIPE_FORMAT_L8_SRGB:
case PIPE_FORMAT_R8_UNORM:
case PIPE_FORMAT_R8_SNORM:
+ case PIPE_FORMAT_R8_UINT:
+ case PIPE_FORMAT_R8_SINT:
return V_028C70_COLOR_8;
/* 16-bit buffers. */
return V_028C70_COLOR_16;
case PIPE_FORMAT_L8A8_UNORM:
+ case PIPE_FORMAT_L8A8_UINT:
+ case PIPE_FORMAT_L8A8_SINT:
case PIPE_FORMAT_L8A8_SRGB:
case PIPE_FORMAT_R8G8_UNORM:
+ case PIPE_FORMAT_R8G8_UINT:
+ case PIPE_FORMAT_R8G8_SINT:
return V_028C70_COLOR_8_8;
case PIPE_FORMAT_R16_UNORM:
+ case PIPE_FORMAT_R16_UINT:
+ case PIPE_FORMAT_R16_SINT:
return V_028C70_COLOR_16;
case PIPE_FORMAT_R16_FLOAT:
case PIPE_FORMAT_X8B8G8R8_UNORM:
case PIPE_FORMAT_X8R8G8B8_UNORM:
case PIPE_FORMAT_R8G8B8_UNORM:
+ case PIPE_FORMAT_R8G8B8A8_SSCALED:
+ case PIPE_FORMAT_R8G8B8A8_USCALED:
+ case PIPE_FORMAT_R8G8B8A8_SINT:
+ case PIPE_FORMAT_R8G8B8A8_UINT:
return V_028C70_COLOR_8_8_8_8;
case PIPE_FORMAT_R10G10B10A2_UNORM:
case PIPE_FORMAT_R10G10B10X2_SNORM:
case PIPE_FORMAT_B10G10R10A2_UNORM:
+ case PIPE_FORMAT_B10G10R10A2_UINT:
case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
return V_028C70_COLOR_2_10_10_10;
case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
return V_028C70_COLOR_8_24;
case PIPE_FORMAT_X8Z24_UNORM:
- case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
return V_028C70_COLOR_24_8;
- case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
return V_028C70_COLOR_X24_8_32_FLOAT;
+ case PIPE_FORMAT_R32_UINT:
+ case PIPE_FORMAT_R32_SINT:
+ return V_028C70_COLOR_32;
+
case PIPE_FORMAT_R32_FLOAT:
case PIPE_FORMAT_Z32_FLOAT:
return V_028C70_COLOR_32_FLOAT;
case PIPE_FORMAT_R16G16_SSCALED:
case PIPE_FORMAT_R16G16_UNORM:
+ case PIPE_FORMAT_R16G16_UINT:
+ case PIPE_FORMAT_R16G16_SINT:
return V_028C70_COLOR_16_16;
case PIPE_FORMAT_R11G11B10_FLOAT:
/* 64-bit buffers. */
case PIPE_FORMAT_R16G16B16_USCALED:
- case PIPE_FORMAT_R16G16B16A16_USCALED:
case PIPE_FORMAT_R16G16B16_SSCALED:
+ case PIPE_FORMAT_R16G16B16A16_UINT:
+ case PIPE_FORMAT_R16G16B16A16_SINT:
+ case PIPE_FORMAT_R16G16B16A16_USCALED:
case PIPE_FORMAT_R16G16B16A16_SSCALED:
case PIPE_FORMAT_R16G16B16A16_UNORM:
case PIPE_FORMAT_R16G16B16A16_SNORM:
case PIPE_FORMAT_R32G32_USCALED:
case PIPE_FORMAT_R32G32_SSCALED:
+ case PIPE_FORMAT_R32G32_SINT:
+ case PIPE_FORMAT_R32G32_UINT:
return V_028C70_COLOR_32_32;
/* 96-bit buffers. */
/* 128-bit buffers. */
case PIPE_FORMAT_R32G32B32A32_SNORM:
case PIPE_FORMAT_R32G32B32A32_UNORM:
+ case PIPE_FORMAT_R32G32B32A32_SSCALED:
+ case PIPE_FORMAT_R32G32B32A32_USCALED:
+ case PIPE_FORMAT_R32G32B32A32_SINT:
+ case PIPE_FORMAT_R32G32B32A32_UINT:
return V_028C70_COLOR_32_32_32_32;
case PIPE_FORMAT_R32G32B32A32_FLOAT:
return V_028C70_COLOR_32_32_32_32_FLOAT;
{
if (R600_BIG_ENDIAN) {
switch(colorformat) {
- case V_028C70_COLOR_4_4:
- return ENDIAN_NONE;
/* 8-bit buffers. */
case V_028C70_COLOR_8:
blend->cb_target_mask = target_mask;
r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
- color_control, 0xFFFFFFFD, NULL, 0);
+ color_control, 0xFFFFFFFF, NULL, 0);
if (rctx->chip_class != CAYMAN)
r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
- unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
- unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
+ unsigned db_depth_control, alpha_test_control, alpha_ref;
+ unsigned db_render_override, db_render_control;
struct r600_pipe_state *rstate;
if (dsa == NULL) {
return NULL;
}
+ dsa->valuemask[0] = state->stencil[0].valuemask;
+ dsa->valuemask[1] = state->stencil[1].valuemask;
+ dsa->writemask[0] = state->stencil[0].writemask;
+ dsa->writemask[1] = state->stencil[1].writemask;
+
rstate = &dsa->rstate;
rstate->id = R600_PIPE_STATE_DSA;
- /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
- db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
- stencil_ref_mask = 0;
- stencil_ref_mask_bf = 0;
db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
S_028800_ZFUNC(state->depth.func);
db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
-
- stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
- S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
if (state->stencil[1].enabled) {
db_depth_control |= S_028800_BACKFACE_ENABLE(1);
db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
- stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
- S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
}
}
r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(rstate,
- R_028430_DB_STENCILREFMASK, stencil_ref_mask,
- 0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
- r600_pipe_state_add_reg(rstate,
- R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
- 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
/* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
* STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
* evergreen_pipe_shader_ps().*/
- r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL, 0);
unsigned tmp;
unsigned prov_vtx = 1, polygon_dual_mode;
unsigned clip_rule;
+ float psize_min, psize_max;
if (rs == NULL) {
return NULL;
}
rstate = &rs->rstate;
- rs->clamp_vertex_color = state->clamp_vertex_color;
- rs->clamp_fragment_color = state->clamp_fragment_color;
rs->flatshade = state->flatshade;
rs->sprite_coord_enable = state->sprite_coord_enable;
+ rs->two_side = state->light_twoside;
+ rs->clip_plane_enable = state->clip_plane_enable;
clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
state->fill_back != PIPE_POLYGON_MODE_FILL);
r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
S_028814_PROVOKING_VTX_LAST(prov_vtx) |
- S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
- S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
+ S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
+ S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
S_028814_FACE(!state->front_ccw) |
S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
S_028814_POLY_MODE(polygon_dual_mode) |
S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
- S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
- S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
/* point size 12.4 fixed point */
tmp = (unsigned)(state->point_size * 8.0);
r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL, 0);
+
+ if (state->point_size_per_vertex) {
+ psize_min = util_get_min_point_size(state);
+ psize_max = 8192;
+ } else {
+ /* Force the point size to be as if the vertex output was disabled. */
+ psize_min = state->point_size;
+ psize_max = state->point_size;
+ }
+ /* Divide by two, because 0.5 = 1 pixel. */
+ r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
+ S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
+ S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
+ 0xFFFFFFFF, NULL, 0);
tmp = (unsigned)state->line_width * 8;
r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
+ if (state->line_stipple_enable) {
+ r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE,
+ S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
+ S_028A0C_REPEAT_COUNT(state->line_stipple_factor),
+ 0x9FFFFFFF, NULL, 0);
+ }
+
+ r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
+ S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
+ 0xFFFFFFFF, NULL, 0);
+
if (rctx->chip_class == CAYMAN) {
r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
0xFFFFFFFF, NULL, 0);
}
- r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
+ S_028810_PS_UCP_MODE(3) | S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
+ S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
+ S_028810_DX_LINEAR_ATTR_CLIP_ENA(1),
+ ~(C_028810_PS_UCP_MODE & C_028810_ZCLIP_NEAR_DISABLE &
+ C_028810_ZCLIP_FAR_DISABLE &
+ C_028810_DX_LINEAR_ATTR_CLIP_ENA), NULL, 0);
return rstate;
}
}
rstate->id = R600_PIPE_STATE_SAMPLER;
- util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
+ util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
0xFFFFFFFF, NULL, 0);
if (uc.ui) {
- r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), 0xFFFFFFFF, NULL, 0);
}
return rstate;
}
struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
struct r600_pipe_resource_state *rstate;
struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
- struct r600_resource *rbuffer;
unsigned format, endian;
uint32_t word4 = 0, yuv_format = 0, pitch = 0;
unsigned char swizzle[4], array_mode = 0, tile_type = 0;
- struct r600_bo *bo[2];
+ unsigned height, depth;
if (view == NULL)
return NULL;
endian = r600_colorformat_endian_swap(format);
- if (tmp->force_int_type) {
- word4 &= C_030010_NUM_FORMAT_ALL;
- word4 |= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT);
- }
-
- rbuffer = &tmp->resource;
- bo[0] = rbuffer->bo;
- bo[1] = rbuffer->bo;
+ height = texture->height0;
+ depth = texture->depth0;
- pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
+ pitch = align(tmp->pitch_in_blocks[0] *
+ util_format_get_blockwidth(state->format), 8);
array_mode = tmp->array_mode[0];
tile_type = tmp->tile_type;
- rstate->bo[0] = bo[0];
- rstate->bo[1] = bo[1];
+ if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
+ height = 1;
+ depth = texture->array_size;
+ } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
+ depth = texture->array_size;
+ }
+
+ rstate->bo[0] = &tmp->resource;
+ rstate->bo[1] = &tmp->resource;
rstate->bo_usage[0] = RADEON_USAGE_READ;
rstate->bo_usage[1] = RADEON_USAGE_READ;
+
rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
S_030000_PITCH((pitch / 8) - 1) |
S_030000_NON_DISP_TILING_ORDER(tile_type) |
S_030000_TEX_WIDTH(texture->width0 - 1));
- rstate->val[1] = (S_030004_TEX_HEIGHT(texture->height0 - 1) |
- S_030004_TEX_DEPTH(texture->depth0 - 1) |
+ rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
+ S_030004_TEX_DEPTH(depth - 1) |
S_030004_ARRAY_MODE(array_mode));
- rstate->val[2] = tmp->offset[0] >> 8;
- rstate->val[3] = tmp->offset[1] >> 8;
+ rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
+ rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
rstate->val[4] = (word4 |
S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
S_030010_ENDIAN_SWAP(endian) |
S_030010_BASE_LEVEL(state->u.tex.first_level));
rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
- S_030014_BASE_ARRAY(0) |
- S_030014_LAST_ARRAY(0));
+ S_030014_BASE_ARRAY(state->u.tex.first_layer) |
+ S_030014_LAST_ARRAY(state->u.tex.last_layer));
rstate->val[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
rstate->val[7] = (S_03001C_DATA_FORMAT(format) |
S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE));
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+ struct pipe_resource *cbuf;
if (rstate == NULL)
return;
rctx->clip = *state;
rstate->id = R600_PIPE_STATE_CLIP;
- for (int i = 0; i < state->nr; i++) {
+ for (int i = 0; i < 6; i++) {
r600_pipe_state_add_reg(rstate,
R_0285BC_PA_CL_UCP0_X + i * 16,
fui(state->ucp[i][0]), 0xFFFFFFFF, NULL, 0);
R_0285C8_PA_CL_UCP0_W + i * 16,
fui(state->ucp[i][3]), 0xFFFFFFFF, NULL, 0);
}
- r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
- S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
- S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
- S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL, 0);
free(rctx->states[R600_PIPE_STATE_CLIP]);
rctx->states[R600_PIPE_STATE_CLIP] = rstate;
r600_context_pipe_state_set(&rctx->ctx, rstate);
+
+ cbuf = pipe_user_buffer_create(ctx->screen,
+ state->ucp,
+ 4*4*8, /* 8*4 floats */
+ PIPE_BIND_CONSTANT_BUFFER);
+ r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
+ pipe_resource_reference(&cbuf, NULL);
}
static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
r600_context_pipe_state_set(&rctx->ctx, rstate);
}
-static void evergreen_set_stencil_ref(struct pipe_context *ctx,
- const struct pipe_stencil_ref *state)
-{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
- struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- u32 tmp;
-
- if (rstate == NULL)
- return;
-
- rctx->stencil_ref = *state;
- rstate->id = R600_PIPE_STATE_STENCIL_REF;
- tmp = S_028430_STENCILREF(state->ref_value[0]);
- r600_pipe_state_add_reg(rstate,
- R_028430_DB_STENCILREFMASK, tmp,
- ~C_028430_STENCILREF, NULL, 0);
- tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
- r600_pipe_state_add_reg(rstate,
- R_028434_DB_STENCILREFMASK_BF, tmp,
- ~C_028434_STENCILREF_BF, NULL, 0);
-
- free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
- rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
- r600_context_pipe_state_set(&rctx->ctx, rstate);
-}
-
static void evergreen_set_viewport_state(struct pipe_context *ctx,
const struct pipe_viewport_state *state)
{
const struct pipe_framebuffer_state *state, int cb)
{
struct r600_resource_texture *rtex;
- struct r600_resource *rbuffer;
struct r600_surface *surf;
unsigned level = state->cbufs[cb]->u.tex.level;
unsigned pitch, slice;
unsigned color_info;
unsigned format, swap, ntype, endian;
- unsigned offset;
+ uint64_t offset;
unsigned tile_type;
const struct util_format_description *desc;
- struct r600_bo *bo[3];
int i;
+ unsigned blend_clamp = 0, blend_bypass = 0;
surf = (struct r600_surface *)state->cbufs[cb];
rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
rtex = rtex->flushed_depth_texture;
}
- rbuffer = &rtex->resource;
- bo[0] = rbuffer->bo;
- bo[1] = rbuffer->bo;
- bo[2] = rbuffer->bo;
-
/* XXX quite sure for dx10+ hw don't need any offset hacks */
- offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
+ offset = r600_texture_get_offset(rtex,
level, state->cbufs[cb]->u.tex.first_layer);
pitch = rtex->pitch_in_blocks[level] / 8 - 1;
slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
break;
}
}
+
ntype = V_028C70_NUMBER_UNORM;
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
ntype = V_028C70_NUMBER_SRGB;
- else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
- ntype = V_028C70_NUMBER_SNORM;
+ else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
+ if (desc->channel[i].normalized)
+ ntype = V_028C70_NUMBER_SNORM;
+ else if (desc->channel[i].pure_integer)
+ ntype = V_028C70_NUMBER_SINT;
+ } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
+ if (desc->channel[i].normalized)
+ ntype = V_028C70_NUMBER_UNORM;
+ else if (desc->channel[i].pure_integer)
+ ntype = V_028C70_NUMBER_UINT;
+ }
format = r600_translate_colorformat(surf->base.format);
swap = r600_translate_colorswap(surf->base.format);
- if (rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
+ if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
endian = ENDIAN_NONE;
} else {
endian = r600_colorformat_endian_swap(format);
}
- /* disable when gallium grows int textures */
- if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
- ntype = V_028C70_NUMBER_UINT;
+ /* blend clamp should be set for all NORM/SRGB types */
+ if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
+ ntype == V_028C70_NUMBER_SRGB)
+ blend_clamp = 1;
+
+ /* set blend bypass according to docs if SINT/UINT or
+ 8/24 COLOR variants */
+ if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
+ format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
+ format == V_028C70_COLOR_X24_8_32_FLOAT) {
+ blend_clamp = 0;
+ blend_bypass = 1;
+ }
color_info = S_028C70_FORMAT(format) |
S_028C70_COMP_SWAP(swap) |
S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
- S_028C70_BLEND_CLAMP(1) |
+ S_028C70_BLEND_CLAMP(blend_clamp) |
+ S_028C70_BLEND_BYPASS(blend_bypass) |
S_028C70_NUMBER_TYPE(ntype) |
S_028C70_ENDIAN(endian);
-
/* EXPORT_NORM is an optimzation that can be enabled for better
* performance in certain cases.
* EXPORT_NORM can be enabled if:
} else /* workaround for linear buffers */
tile_type = 1;
+ offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
+ offset >>= 8;
+
/* FIXME handle enabling of CB beyond BASE8 which has different offset */
r600_pipe_state_add_reg(rstate,
R_028C60_CB_COLOR0_BASE + cb * 0x3C,
- offset >> 8, 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE);
+ offset, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate,
R_028C78_CB_COLOR0_DIM + cb * 0x3C,
0x0, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate,
R_028C70_CB_COLOR0_INFO + cb * 0x3C,
- color_info, 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE);
+ color_info, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate,
R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
S_028C64_PITCH_TILE_MAX(pitch),
r600_pipe_state_add_reg(rstate,
R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
S_028C74_NON_DISP_TILING_ORDER(tile_type),
- 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE);
+ 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
}
static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
{
struct r600_resource_texture *rtex;
struct r600_surface *surf;
- unsigned level, first_layer;
- unsigned pitch, slice, format;
- unsigned offset;
+ unsigned level, first_layer, pitch, slice, format, array_mode;
+ uint64_t offset;
if (state->zsbuf == NULL)
return;
surf = (struct r600_surface *)state->zsbuf;
+ level = surf->base.u.tex.level;
rtex = (struct r600_resource_texture*)surf->base.texture;
- level = surf->base.u.tex.level;
+ /* XXX remove this once tiling is properly supported */
+ array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
+ V_028C70_ARRAY_1D_TILED_THIN1;
+
first_layer = surf->base.u.tex.first_layer;
offset = r600_texture_get_offset(rtex, level, first_layer);
pitch = rtex->pitch_in_blocks[level] / 8 - 1;
slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
format = r600_translate_dbformat(rtex->real_format);
+ offset += r600_resource_va(rctx->context.screen, surf->base.texture);
+ offset >>= 8;
+
r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
- offset >> 8, 0xFFFFFFFF, rtex->resource.bo, RADEON_USAGE_READWRITE);
+ offset, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
- offset >> 8, 0xFFFFFFFF, rtex->resource.bo, RADEON_USAGE_READWRITE);
+ offset, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
if (rtex->stencil) {
- uint32_t stencil_offset =
+ uint64_t stencil_offset =
r600_texture_get_offset(rtex->stencil, level, first_layer);
+ stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
+ stencil_offset >>= 8;
+
r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
- stencil_offset >> 8, 0xFFFFFFFF, rtex->stencil->resource.bo, RADEON_USAGE_READWRITE);
+ stencil_offset, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
- stencil_offset >> 8, 0xFFFFFFFF, rtex->stencil->resource.bo, RADEON_USAGE_READWRITE);
+ stencil_offset, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
- 1, 0xFFFFFFFF, rtex->stencil->resource.bo, RADEON_USAGE_READWRITE);
+ 1, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
} else {
r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
0, 0xFFFFFFFF, NULL, RADEON_USAGE_READWRITE);
}
r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
- S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
- 0xFFFFFFFF, rtex->resource.bo, RADEON_USAGE_READWRITE);
+ S_028040_ARRAY_MODE(array_mode) | S_028040_FORMAT(format),
+ 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
S_028058_PITCH_TILE_MAX(pitch),
0xFFFFFFFF, NULL, 0);
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- u32 shader_mask, tl, br, target_mask;
+ u32 shader_mask, tl, br;
int tl_x, tl_y, br_x, br_y;
if (rstate == NULL)
rctx->ctx.num_dest_buffers++;
}
- target_mask = 0x00000000;
- target_mask = 0xFFFFFFFF;
shader_mask = 0;
for (int i = 0; i < state->nr_cbufs; i++) {
- target_mask ^= 0xf << (i * 4);
shader_mask |= 0xf << (i * 4);
}
tl_x = 0;
r600_pipe_state_add_reg(rstate,
R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
0xFFFFFFFF, NULL, 0);
-
- r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
- 0x00000000, target_mask, NULL, 0);
r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
shader_mask, 0xFFFFFFFF, NULL, 0);
} else {
r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
0x00000000, 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
+ r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0,
0x00000000, 0xFFFFFFFF, NULL, 0);
}
rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
rctx->context.set_sample_mask = evergreen_set_sample_mask;
rctx->context.set_scissor_state = evergreen_set_scissor_state;
- rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
+ rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
rctx->context.set_index_buffer = r600_set_index_buffer;
rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
rctx->context.texture_barrier = evergreen_texture_barrier;
+ rctx->context.create_stream_output_target = r600_create_so_target;
+ rctx->context.stream_output_target_destroy = r600_so_target_destroy;
+ rctx->context.set_stream_output_targets = r600_set_so_targets;
}
static void cayman_init_config(struct r600_pipe_context *rctx)
r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg(rstate, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
/* enable dynamic GPR resource management */
- if (r600_get_minor_version(rctx->radeon) >= 7) {
+ if (rctx->screen->info.drm_minor >= 7) {
/* always set temp clauses */
r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL, 0);
#endif
- r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
switch (rctx->framebuffer.zsbuf->texture->format) {
case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
depth = -24;
offset_units *= 2.0f;
break;
case PIPE_FORMAT_Z32_FLOAT:
- case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
depth = -23;
offset_units *= 1.0f;
offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
int pos_index = -1, face_index = -1;
int ninterp = 0;
boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
- unsigned spi_baryc_cntl;
+ unsigned spi_baryc_cntl, sid, tmp, idx = 0;
rstate->nregs = 0;
- db_shader_control = 0;
+ db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
for (i = 0; i < rshader->ninput; i++) {
/* evergreen NUM_INTERP only contains values interpolated into the LDS,
POSITION goes via GPRs from the SC so isn't counted */
else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
face_index = i;
else {
- if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
- rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
- ninterp++;
+ ninterp++;
if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
have_linear = TRUE;
if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
if (rshader->input[i].centroid)
have_centroid = TRUE;
}
+
+ sid = rshader->input[i].spi_sid;
+
+ if (sid) {
+
+ tmp = S_028644_SEMANTIC(sid);
+
+ if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
+ rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
+ (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
+ rctx->rasterizer && rctx->rasterizer->flatshade)) {
+ tmp |= S_028644_FLAT_SHADE(1);
+ }
+
+ if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
+ (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
+ tmp |= S_028644_PT_SPRITE_TEX(1);
+ }
+
+ r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
+ tmp, 0xFFFFFFFF, NULL, 0);
+
+ idx++;
+ }
}
+
for (i = 0; i < rshader->noutput; i++) {
if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
have_perspective = TRUE;
}
+ if (!have_perspective && !have_linear)
+ have_perspective = TRUE;
+
spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
r600_pipe_state_add_reg(rstate,
R_028840_SQ_PGM_START_PS,
- 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
+ r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
+ 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
r600_pipe_state_add_reg(rstate,
R_028844_SQ_PGM_RESOURCES_PS,
S_028844_NUM_GPRS(rshader->bc.ngpr) |
0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate,
R_028848_SQ_PGM_RESOURCES_2_PS,
- 0x0, 0xFFFFFFFF, NULL, 0);
+ S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
+ 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate,
R_02884C_SQ_PGM_EXPORTS_PS,
exports_ps, 0xFFFFFFFF, NULL, 0);
- /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
- /* only set some bits here, the other bits are set in the dsa state */
- r600_pipe_state_add_reg(rstate,
- R_02880C_DB_SHADER_CONTROL,
+ r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
db_shader_control,
- S_02880C_Z_EXPORT_ENABLE(1) |
- S_02880C_STENCIL_EXPORT_ENABLE(1) |
- S_02880C_KILL_ENABLE(1),
- NULL, 0);
+ 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate,
R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
0xFFFFFFFF, NULL, 0);
+
+ shader->sprite_coord_enable = rctx->sprite_coord_enable;
+ if (rctx->rasterizer)
+ shader->flatshade = rctx->rasterizer->flatshade;
}
void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = &shader->rstate;
struct r600_shader *rshader = &shader->shader;
- unsigned spi_vs_out_id[10];
- unsigned i, tmp, nparams;
+ unsigned spi_vs_out_id[10] = {};
+ unsigned i, tmp, nparams = 0;
/* clear previous register */
rstate->nregs = 0;
- /* so far never got proper semantic id from tgsi */
- for (i = 0; i < 10; i++) {
- spi_vs_out_id[i] = 0;
- }
- for (i = 0; i < 32; i++) {
- tmp = i << ((i & 3) * 8);
- spi_vs_out_id[i / 4] |= tmp;
+ for (i = 0; i < rshader->noutput; i++) {
+ if (rshader->output[i].spi_sid) {
+ tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
+ spi_vs_out_id[nparams / 4] |= tmp;
+ nparams++;
+ }
}
+
for (i = 0; i < 10; i++) {
r600_pipe_state_add_reg(rstate,
R_02861C_SPI_VS_OUT_ID_0 + i * 4,
* VS is required to export at least one param and r600_shader_from_tgsi()
* takes care of adding a dummy export.
*/
- nparams = rshader->noutput - rshader->npos;
if (nparams < 1)
nparams = 1;
0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate,
R_028864_SQ_PGM_RESOURCES_2_VS,
- 0x0, 0xFFFFFFFF, NULL, 0);
+ S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
+ 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate,
R_02885C_SQ_PGM_START_VS,
- 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
+ r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
+ 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
r600_pipe_state_add_reg(rstate,
R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
0xFFFFFFFF, NULL, 0);
+
+ r600_pipe_state_add_reg(rstate,
+ R_02881C_PA_CL_VS_OUT_CNTL,
+ S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
+ S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
+ S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
+ S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size),
+ S_02881C_VS_OUT_CCDIST0_VEC_ENA(1) |
+ S_02881C_VS_OUT_CCDIST1_VEC_ENA(1) |
+ S_02881C_VS_OUT_MISC_VEC_ENA(1) |
+ S_02881C_USE_VTX_POINT_SIZE(1),
+ NULL, 0);
}
void evergreen_fetch_shader(struct pipe_context *ctx,
r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
0x00000000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
- 0,
+ r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
0xFFFFFFFF, ve->fetch_shader, RADEON_USAGE_READ);
}
memset(&dsa, 0, sizeof(dsa));
rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
- r600_pipe_state_add_reg(rstate,
- R_02880C_DB_SHADER_CONTROL,
- 0x0,
- S_02880C_DUAL_EXPORT_ENABLE(1), NULL, 0);
r600_pipe_state_add_reg(rstate,
R_028000_DB_RENDER_CONTROL,
S_028000_DEPTH_COPY_ENABLE(1) |
S_028000_STENCIL_COPY_ENABLE(1) |
S_028000_COPY_CENTROID(1),
- S_028000_DEPTH_COPY_ENABLE(1) |
- S_028000_STENCIL_COPY_ENABLE(1) |
- S_028000_COPY_CENTROID(1), NULL, 0);
+ 0xFFFFFFFF, NULL, 0);
return rstate;
}
}
-void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
+void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
+ struct r600_pipe_resource_state *rstate,
struct r600_resource *rbuffer,
unsigned offset, unsigned stride,
enum radeon_bo_usage usage)
{
- rstate->bo[0] = rbuffer->bo;
+ uint64_t va;
+
+ va = r600_resource_va(ctx->screen, (void *)rbuffer);
+ rstate->bo[0] = rbuffer;
rstate->bo_usage[0] = usage;
- rstate->val[0] = offset;
- rstate->val[1] = rbuffer->bo_size - offset - 1;
+ rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
+ rstate->val[1] = rbuffer->buf->size - offset - 1;
rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
- S_030008_STRIDE(stride);
+ S_030008_STRIDE(stride) |
+ (((va + offset) >> 32UL) & 0xFF);
}
projects / mesa.git / blobdiff