r600g: fix up vs export handling

[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 97f10ce77b90c4bc117b4f8f25571955c8a6053c..bc6039dd40c72d99d61b5a90eaf928f994bc3c5b 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -510,11 +510,11 @@ static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
        if (R600_BIG_ENDIAN) {
                switch(colorformat) {
                case V_028C70_COLOR_4_4:
-                       return(ENDIAN_NONE);
+                       return ENDIAN_NONE;
 
                /* 8-bit buffers. */
                case V_028C70_COLOR_8:
-                       return(ENDIAN_NONE);
+                       return ENDIAN_NONE;
 
                /* 16-bit buffers. */
                case V_028C70_COLOR_5_6_5:
@@ -522,7 +522,7 @@ static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
                case V_028C70_COLOR_4_4_4_4:
                case V_028C70_COLOR_16:
                case V_028C70_COLOR_8_8:
-                       return(ENDIAN_8IN16);
+                       return ENDIAN_8IN16;
 
                /* 32-bit buffers. */
                case V_028C70_COLOR_8_8_8_8:
@@ -532,23 +532,23 @@ static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
                case V_028C70_COLOR_32_FLOAT:
                case V_028C70_COLOR_16_16_FLOAT:
                case V_028C70_COLOR_16_16:
-                       return(ENDIAN_8IN32);
+                       return ENDIAN_8IN32;
 
                /* 64-bit buffers. */
                case V_028C70_COLOR_16_16_16_16:
                case V_028C70_COLOR_16_16_16_16_FLOAT:
-                       return(ENDIAN_8IN16);
+                       return ENDIAN_8IN16;
 
                case V_028C70_COLOR_32_32_FLOAT:
                case V_028C70_COLOR_32_32:
-                       return(ENDIAN_8IN32);
+                       return ENDIAN_8IN32;
 
                /* 96-bit buffers. */
                case V_028C70_COLOR_32_32_32_FLOAT:
                /* 128-bit buffers. */
                case V_028C70_COLOR_32_32_32_32_FLOAT:
                case V_028C70_COLOR_32_32_32_32:
-                       return(ENDIAN_8IN32);
+                       return ENDIAN_8IN32;
                default:
                        return ENDIAN_NONE; /* Unsupported. */
                }
@@ -2026,6 +2026,11 @@ void evergreen_init_config(struct r600_pipe_context *rctx)
        tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
        r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
 
+       tmp = 0;
+       tmp |= S_008E2C_NUM_PS_LDS(0x1000);
+       tmp |= S_008E2C_NUM_LS_LDS(0x1000);
+       r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
+
        r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
 
@@ -2293,7 +2298,7 @@ void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader
        struct r600_pipe_state *rstate = &shader->rstate;
        struct r600_shader *rshader = &shader->shader;
        unsigned spi_vs_out_id[10];
-       unsigned i, tmp;
+       unsigned i, tmp, nparams;
 
        /* clear previous register */
        rstate->nregs = 0;
@@ -2312,9 +2317,17 @@ void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader
                                        spi_vs_out_id[i], 0xFFFFFFFF, NULL);
        }
 
+       /* Certain attributes (position, psize, etc.) don't count as params.
+        * VS is required to export at least one param and r600_shader_from_tgsi()
+        * takes care of adding a dummy export.
+        */
+       nparams = rshader->noutput - rshader->npos;
+       if (nparams < 1)
+               nparams = 1;
+
        r600_pipe_state_add_reg(rstate,
                        R_0286C4_SPI_VS_OUT_CONFIG,
-                       S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
+                       S_0286C4_VS_EXPORT_COUNT(nparams - 1),
                        0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate,
                        R_028860_SQ_PGM_RESOURCES_VS,